HY5DU283222AQ-5 Hynix Semiconductor, HY5DU283222AQ-5 Datasheet
HY5DU283222AQ-5
Specifications of HY5DU283222AQ-5
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HY5DU283222AQ-5 Summary of contents
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... GDDR SDRAM This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any re- sponsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / Sep. 2003 HY5DU283222AQ HY5DU283222AQ 1 ...
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... Revision History Revision No. 0.1 Defined target Spec. Insert AC Overshoot/ Undershoot Specification 0.2 Insert tDSS/ tDSH parameter Rev. 0.2 / Sep. 2003 History HY5DU283222AQ Draft Date Remark Apr. 2003 Preliminary Sep. 2003 2 ...
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... Power up sequence and Device Initialization 5.3 MRS/EMRS definition 5.4 Device Operation 6. Absolute Maximum Rating -------------------------------------------------------------------------------- 7. DC Operating Condition ------------------------------------------------------------------------------------- 8. DC Characteristics -------------------------------------------------------------------------------------------- 9. AC Operating Test Condition ------------------------------------------------------------------------------ 10. AC Characteristics ------------------------------------------------------------------------------------------ 11. Input /Output Capacitance & Output Load Circuit ---------------------------------------------- 12. Timing Diagram --------------------------------------------------------------------------------------------- Rev. 0.2 / Sep. 2003 CONTENTS HY5DU283222AQ ...
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... Part No. Power Supply HY5DU283222AQ-33 HY5DU283222AQ-36 V DD/ = 2.5V HY5DU283222AQ-4 HY5DU283222AQ-5 Rev. 0.2 / Sep. 2003 • All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock • Write mask byte controls by DM (DM0 ~ DM3) • ...
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... VDDQ 22 DM0 23 DM2 24 /WE 25 /CAS 26 /RAS 27 /CS 28 BA0 29 BA1 30 Auto Precharge Flag Rev. 0.2 / Sep. 2003 TOP VIEW 20mm x 14mm 100 Pin QFP 0.65mm Pitch ROW and COLUMN ADDRESS TABLE Items Organization Row Address Column Address Bank Address Refresh HY5DU283222AQ 4Mx32 ...
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... Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in write data. Used to capture write data. Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. HY5DU283222AQ 6 ...
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... Low Quad Flat Package 22.10(0.870) 21.90(0.862) 20.10(0.791) 19.90(0.783) 1.60(0.063) 1.45(0.057) All dimension in mm (inches). Notation is Rev. 0.2 / Sep. 2003 Unit:mm(inch) Base Plane Seating Plane MAX or typical. MIN HY5DU283222AQ Detail A Gauge Line 0.15(0.006) 0.20(0.008) 0.05(0.002) 0.09(0.004) 0~7 Deg 0.75(0.029) 0.50(0.020) 0.66(0.026) 0.45(0.018) 1.00(0.0394)REF 7 ...
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... Rev. 0.2 / Sep. 2003 Write Data Register 2-bit Prefetch Unit 64 Bank 1Mx32/Bank0 Control 1Mx32 /Bank1 1Mx32 /Bank2 1Mx32 /Bank3 Mode Row Register Decoder Column Decoder Column Address Counter CLK_DLL CLK, DLL /CLK Block Mode Register HY5DU283222AQ DQ[0:31] DQS Data Strobe Transmitter Data Strobe DS Receiver 8 ...
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... If A8/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. Rev. 0.2 / Sep. 2003 CKEn CS RAS HY5DU283222AQ A8/ CAS WE ADDR code code Note 1 1,4 X ...
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... Write Mask command masks burst write data with reference to DQS(Data Strobes) and it is not related with read data. 2. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the data on DQ24-Q31. Rev. 0.2 / Sep. 2003 CKEn CS, RAS, CAS HY5DU283222AQ A8/ DM(0~3) BA ADDR ...
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... BA OPCODE BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP HY5DU283222AQ Command Action DSEL NOP or power down NOP NOP or power down BST ILLEGAL ILLEGAL ILLEGAL ACT Row Activation PRE/PALL NOP AREF/SREF Auto Refresh or Self Refresh MRS Mode Register Set DSEL NOP NOP NOP BST ILLEGAL ...
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... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DU283222AQ Command Action ACT ILLEGAL PRE/PALL Term burst, precharge AREF/SREF ILLEGAL MRS ILLEGAL DSEL Continue burst to end NOP Continue burst to end BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL ...
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... L BA OPCODE BA, CA, AP READ/READAP HY5DU283222AQ Command Action DSEL NOP - Enter ROW ACT after tRCD NOP NOP - Enter ROW ACT after tRCD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter ROW ACT after tWR NOP ...
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... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DU283222AQ Command Action ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter IDLE after tMRD NOP NOP - Enter IDLE after tMRD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ...
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... HY5DU283222AQ /ADD Action X INVALID X Exit self refresh, enter idle after tSREX X Exit self refresh, enter idle after tSREX X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue self refresh X INVALID X Exit power down, enter idle X Exit power down, enter idle X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue power down mode ...
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... IDLE SREX PDEN PDEX AREF ACT POWER DOWN PDEN PDEX BANK ACTIVE WRITE READ WITH WITH AUTOPRE- AUTOPRE- CHARGE CHARGE WRITE PRE- CHARGE POWER-UP POWER APPLIED HY5DU283222AQ SELF REFRESH AUTO REFRESH BST READ READAP READ WRITEAP PRE(PALL) Command Input Automatic Sequence 16 ...
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... V in the following power up sequencing and attempt to maintain CKE at LVC- REF supply into any pin. Sequencing Voltage relationship to avoid latch-up After or with V DD After or with V DDQ After or with V DDQ HY5DU283222AQ , then and finally DDQ . Except for TT < 0.3V DD < 0.3V DDQ < ...
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... CODE CODE CODE tRP tMRD tMRD EMRS Set MRS Set Precharge All Precharge All Reset DLL (with A8=H) * 200 cycle(tXSRD are required (for DLL locking) before Read Command HY5DU283222AQ AREF MRS ACT CODE CODE CODE CODE CODE CODE tRP tRFC tMRD ...
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... CAS Latency BT A7 Test Mode 0 Normal Vendor 1 test mode A8 DLL Reset Yes CAS Latency Reserved Reserved Reserved Reserved Reserved Reserved HY5DU283222AQ Burst Length Burst Length Sequential Reserved Reserved Reserved Reserved Reserved A3 Burst Type 0 Sequential 1 Interleave Interleave Reserved Reserved Reserved Reserved Reserved ...
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... A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definitionon Table Rev. 0.2 / Sep. 2003 Sequential XX0 0, 1 XX1 1, 0 X00 X01 X10 X11 000 001 010 011 100 101 110 111 HY5DU283222AQ Interleave ...
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... The HY5DU283222 supports both Half strength driver and Matched impedance driver, intended for lighter load and/or point-to-point environments. Half strength driver is to define about 50% of Full drive strength which is specified to be SSTL_2, Class II, and Matched impedance driver, about 30% of Full drive strength. Rev. 0.2 / Sep. 2003 HY5DU283222AQ 21 ...
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... All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage. Rev. 0.2 / Sep. 2003 RFU HY5DU283222AQ DLL A0 DLL enable 0 Enable 1 Diable A1 Output Driver Impedance Control 0 RFU* 1 Half (60%) 0 RFU* 1 Weak (40%) 0 RFU* 1 Semi Half (50%) 0 RFU* ...
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... Row_A AP Row_A BA Bank 0 /RAS /CAS /WE Activate Bank 0 DM DQS DQ Burst length =4, CAS latency =2 Rev. 0.2 / Sep. 2003 tRRD tRCD CL Col_A Row_B No PCG Row_B Bank 0 Bank 1 Read Activate Bank 0 Bank Bank 0 Data-out HY5DU283222AQ Col_B AutoPCG Bank 1 Write Bank 1 w/ Autopcg Bank 1 Data-in 23 ...
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... Fig.3. is based on tDQSS=0.75*tCK, minimum number of clock of BL/2 for back to back write can be applied when tDQSS=1.25*tCK. Fig.3. Burst Write followed by Burst Write /CLK CLK CMD WRITE (A) tDQSS DQS DQ Burst length =4, CAS latency =2 Rev. 0.2 / Sep. 2003 WRITE ( HY5DU283222AQ EAD (B) data out starts W RITE(B) data in starts 24 ...
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... Fig.5. Burst Write followed by Burst Read /CLK CLK CMD WRITE (A) DQS DQ Burst length =4, CAS latency =2 Rev. 0.2 / Sep. 2003 W R ITE ( READ (B) tDRL HY5DU283222AQ tDRL is counted with respect to CLK rising edge after last falling edge of DQS and DQ data has elapsed ...
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... Fastest Write command to next Write command is determined by /CAS to /CAS delay (tCCD). Timing diagram is shown in Fig.7. Fig.7. Burst Write terminated by another Burst Write / ITE ( ITE ( urst length = latency =2 Rev. 0.2 / Sep. 2003 ead(A) is term inated and R ead(B ) data out starts rite(A) is term inated and W rite(B) data in starts HY5DU283222AQ ...
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... DQ and DQS input are ignored by the DDR SDRAM illegal for a Read command to interrupt a Write with autoprecharge command. Fig.9. Burst Write terminated by another Burst Read /CLK CLK CMD WRITE (A) DQS DQ DM Burst length =4, CAS latency =2 Rev. 0.2 / Sep. 2003 BST (A) W RITE (B) Burst DQS & DQ stop READ (B) Masked HY5DU283222AQ rite data starts ...
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... DQ data has elapsed. Internal precharging action will happen in CLK(n+BL/2+1+tWR) as shown in Fig.11. Fig.11. Burst Write with Autoprecharge /CLK ( urst length = latency =2 Rev. 0.2 / Sep. 2003 B L HY5DU283222AQ arly term ination is illegal here ...
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... Rev. 0.2 / Sep. 2003 tRP Earliest precharge tim e without losing read data PRECHG tDPL tDPL is counted with respect to CLK rising edge after last falling edge of DQS and DQ data has elapsed HY5DU283222AQ AC T tRP ACT Issuing precharge here allows completion of entire burst write 29 ...
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... PRECHG ACT A0 A1 Precharge time can be issued here with tRASmin being met PREC HG tDPL M asked rite burst is term inated early asserted to prevent locations of A2 and A3 HY5DU283222AQ tDPL is counted with respect to CLK rising edge after last falling edge and DQ data has elapsed 30 ...
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... BST command is valid for read operation only. BST latency for read operation is the same as CL. Fig.17. Burst Stop command (Read urst length = latency =2 Rev. 0.2 / Sep. 2003 Masked Masked can mask write data with reference to DQS DM write latency = ( rst & sto HY5DU283222AQ 31 ...
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... DLL circuit of DDR SDRAM. A minimum tPDEX (Power Down Exit Time) must be met before entering SREX command. Fig.19. Self Refresh Entry and Exit /CLK CLK Precharge all CKE Rev. 0.2 / Sep. 2003 tRP tRC = tRAS + tRP AUTOREF ESL HY5DU283222AQ ACT in. 200 clock cycles tXSC tPD EXm in 32 ...
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... Since clock suspend mode in SDR SDRAM cannot be used in DDR SDRAM illegal to issue CKE=L during read or write burst. Fig.21. CKE function /CLK CLK CMD READ (A) DQS DQ CKE Burst length =4, CAS latency =2 Rev. 0.2 / Sep. 2003 PD EN WRITE ( Transition of CKE(to Low) is illegal during Burst Read and W rite HY5DU283222AQ com m and can be issued after Power D own exit ...
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... DD of the transmitting device, and to track variations in the dc level of the same. DDQ ± the dc value. o (TA Voltage referenced to V Symbol Min 0. =0V HY5DU283222AQ Rating -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0 260 ⋅ 0V) SS Max Unit 2.5 2.625 V 2.5 2.625 0.3 V DDQ - ...
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... CKE ≥ V (min), CS ≥ V (min min, Input signals are changed CK one time during 2clks t ≥ t (min), I =0mA All banks active t ≥ t (min), RC RFC All banks active CKE ≤ 0.2V 6 HY5DU283222AQ = 0V) SS Speed Unit 240 210 130 100 450 370 270 3 Note mA ...
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... 0.45 IH(AC) REF V IL(AC) V 0.7 ID(AC) V 0.5*V IX(AC) DDQ of the transmitting device and must track variations in the DC level of the same. DDQ o (TA Voltage referenced to VSS = 0V HY5DU283222AQ = 0V) SS Max Unit 0.45 V REF V + 0.6 V DDQ -0.2 0.5*V +0.2 V DDQ Value Unit V x 0.5 ...
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... The area between the overshoot signal and GND must be less than or equal to(See below Fig) Volt (v) Max. area = 2.4 v-nS Rev. 0.2 / Sep. 2003 Parameter + Time(nS) Parameter + Time(nS) HY5DU283222AQ Specifications 1.5 V 1.5 V 4.5 V-nS 4.5 V-nS Max. Amplitude = 1. Ground 5 6 Specifications 1.2 V 1.2 V 2.4 V-nS 2.4 V-nS Max. Amplitude = 1. Ground ...
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... CH t 0.45 0.55 0. 0 0.7 - 0.7 DQSCK t 0.4 - 0.4 DQSQ tHP- tHP tQHS tQHS tCH/L tCH min min t 0.45 - 0.45 QHS t 0. 0. 0.4 0.6 0.4 DQSH t 0.4 0.6 0.4 DQSL HY5DU283222AQ 4 5 Max Min Max Min Max - ...
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... RPRE t 0.4 0.6 0.4 RPST WPRES t 1.5 - 1.5 WPREH t 0.4 0.8 0.4 WPST MRD t 200 - 200 XSC t - 7.8 - REFI HY5DU283222AQ 4 5 Max Min Max Min Max 1.25 0.75 1.25 0.75 1.25 - 0 0 0 0.2 - 0.2 - 1.1 0.8 1.1 0.8 1 ...
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... These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Output R =25Ω S Rev. 0.2 / Sep. 2003 Pin CK, CK All other input-only pins DQ, DQS /2, V peak-to-peak = 0.2V O DDQ =50Ω R =50Ω Zo=50Ω C =30pF L HY5DU283222AQ Symbol Min Max Unit C 1.7 2 1.7 2 3.7 4 REF ...
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... X consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. Rev. 0.2 / Sep. 2003 tDQSL tDQSH tDH tDS DI n tDH tDS HY5DU283222AQ Don’t care tDQSCK max tQH ...
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... Precharge Power Down. If this command is an ACTIVE ( least one row is already active) then the Power-Down mode shown is Active Power Down. Rev. 0.2 / Sep. 2003 tCH tCL tIS NOP Enter Mode HY5DU283222AQ tIS NOP VALID VALID Exit Power-Down Mode Don’t Care ...
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... NOP commands are shown for ease of illustration ; other valid commands may be possible at these times. DM, DQ and DQS signals are all “Don’t Care” / High-Z for operation shown. Rev. 0.2 / Sep. 2003 tCH tCL AR NOP NOP NOP tRP tRFC HY5DU283222AQ VALID ACT AR NOP NOP tRFC Don’t Care ...
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... CK) are required before a READ command can be applied. Rev. 0.2 / Sep. 2003 clock must be stable before exiting Self Refresh mode tCL tIS AR Enter Mode HY5DU283222AQ tIS NOP VALID tIS tIH VALID tXSNR/ tXSRD** Exit ...
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... NOP ALL BANKS ONE BANK *Bank x tRP tDQSCK min tRPST tRPRE tHZ min Do n tLZ tAC min min tDQSCK max tRPRE tRPST Do n tAC tLZ max max HY5DU283222AQ VALID VALID ACT NOP NOP Bank x tHZ max VALID NOP Don’t Care 45 ...
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... NOP NOP NOP tRP tDQSCK min tRPRE tRPST tHZ min Do n tLZ tAC min min tQPST tDQSCK max tRPRE tRPST Do n tLZ tAC max max HY5DU283222AQ VALID VALID ACT NOP NOP Bank x tHZ max VALID NOP Don’t Care 46 ...
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... Note that tRCD > tRCD min so that the same timing applies if Autoprecharge is enabled (in which case tRAS would be limiting) Rev. 0.2 / Sep. 2003 tCH tCL READ NOP NOP Col n tIS tIH DIS AP Bank x tRC tRAS tRCD HY5DU283222AQ NOP PRE NOP NOP All Bank One Bank Bank x CL=2 tRP tDQSCK min tRPST tRPRE tLZ min ...
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... NOP commands are shown for ease of illustration; other valid commands may be possible at these times Rev. 0.2 / Sep. 2003 tCH tCL NOP NOP NOP tDSH tWPST tDQSL tDSS tDSS tDQSH tWPST tDQSL DI n HY5DU283222AQ Valid PRE NOP NOP All Bank One Bank Bank x tRP tDPL Don’t care ACT ...
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... NOP commands are shown for ease of illustration; other valid commands may be possible at these times Rev. 0.2 / Sep. 2003 tCH tCL VALID NOP NOP NOP tDSH tWPST tDQSL tDSS tDSS tDQSH tWPST tDQSL DI n HY5DU283222AQ VALID VALID ACT NOP NOP NOP tDAL Don’t care RA 49 ...
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... NOP NOP WRITE NOP Col n tIS tIH DIS AP Bank x tRCD tDQSS tDQSH tWPRES tWPRE DI n tDQSS tWPRES tWPRE HY5DU283222AQ NOP NOP NOP tRAS tDPL tDSH tWPST tDQSL tDSS tDSS tDQSH tWPST tDQSL DI n PRE All Banks One bank Bank x Don’t care ...
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... NOP commands are shown for ease of illustration; other valid commands may be possible at these times Rev. 0.2 / Sep. 2003 tCH tCL NOP NOP NOP tDSH tDPL tWPST tDQSL tDSS tDSS tDQSH tWPST tDQSL DI n HY5DU283222AQ VALID PRE NOP NOP All Banks One Bank Bank x tRP Don’t care ACT ...