HY5DU561622CT-6 Hynix Semiconductor, HY5DU561622CT-6 Datasheet
HY5DU561622CT-6
Related parts for HY5DU561622CT-6
HY5DU561622CT-6 Summary of contents
Page 1
... HY5DU561622CT 256M(16Mx16) gDDR SDRAM This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.3 / Feb. 2006 HY5DU561622CT 1 ...
Page 2
... Improvement of VDD from 2.8V to 2.5V in 300MHz 0.3 Changed IDD Spec. 0.4 166MHz Speed added. 0.5 1) Changed VDD Value of HY5DU561622CT-33/36 from 2.5V to 2.6V 0.6 2) Added tRC@Auto Precharge Parameter in AC CHARACTERISTICS - I Added 350MHz Speed 0.7 Changed VDD/VDDQ min/max range of HY5DU561622CT- 33 /36 0.8 ...
Page 3
... HY5DU561622CT-33 VDD=2.6V VDDQ=2.6V HY5DU561622CT-36 HY5DU561622CT-4 VDD=2.5V VDDQ=2.5V HY5DU561622CT-5 HY5DU561622CT-6 Rev. 1.3 / Feb. 2006 Data inputs on DQS centers when write (centered DQ) • Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe • All addresses and control inputs except Data, Data ...
Page 4
... X 875mil 15 66 Pin TSOP 16 0.65mm Pin Pitch ROW and COLUMN ADDRESS TABLE Items Organization Row Address Column Address Bank Address Refresh 1HY5DU561622CT DQ15 64 V SSQ 63 DQ14 62 DQ13 61 V DDQ 60 DQ12 59 DQ11 58 V SSQ 57 DQ10 56 DQ9 55 V DDQ 54 DQ8 ...
Page 5
... Used to capture write data. LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15. Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. 1HY5DU561622CT 5 ...
Page 6
... Rev. 1.3 / Feb. 2006 Write Data Register 2-bit Prefetch Unit Bank 4Mx16/Bank0 Control 4Mx16 /Bank1 4Mx16 /Bank2 4Mx16 /Bank3 Mode Row Register Decoder Column Decoder Column Address Counter CLK, DLL /CLK Block Mode Register 1HY5DU561622CT LDQS,UDQS Data Strobe CLK_DLL Transmitter Data Strobe DS Receiver DS DQ[0:15] 6 ...
Page 7
... If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. Rev. 1.3 / Feb. 2006 CKEn CS RAS 1HY5DU561622CT A10/ CAS WE ADDR code code Note 1 1,4 X ...
Page 8
... Note : 1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. 2. LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively. Rev. 1.3 / Feb. 2006 CKEn /CS, /RAS, /CAS, / 1HY5DU561622CT A10/ LDM UDM ADDR ...
Page 9
... BA OPCODE BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP 1HY5DU561622CT Command Action DSEL NOP or power down NOP NOP or power down BST ILLEGAL ILLEGAL ILLEGAL ACT Row Activation PRE/PALL NOP AREF/SREF Auto Refresh or Self Refresh MRS Mode Register Set DSEL NOP NOP NOP BST ILLEGAL ...
Page 10
... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE 1HY5DU561622CT Command Action ACT ILLEGAL PRE/PALL Term burst, precharge AREF/SREF ILLEGAL MRS ILLEGAL DSEL Continue burst to end NOP Continue burst to end BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL ...
Page 11
... L BA OPCODE BA, CA, AP READ/READAP 1HY5DU561622CT Command Action DSEL NOP - Enter ROW ACT after tRCD NOP NOP - Enter ROW ACT after tRCD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter ROW ACT after tWR NOP ...
Page 12
... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE 1HY5DU561622CT Command Action ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter IDLE after tMRD NOP NOP - Enter IDLE after tMRD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ...
Page 13
... 1HY5DU561622CT /ADD Action X INVALID X Exit self refresh, enter idle after tSREX X Exit self refresh, enter idle after tSREX X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue self refresh X INVALID X Exit power down, enter idle X Exit power down, enter idle X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue power down mode ...
Page 14
... IDLE SREX PDEN PDEX AREF ACT POWER DOWN PDEN PDEX BANK ACTIVE WRITE READ WITH WITH AUTOPRE- AUTOPRE- CHARGE CHARGE WRITE PRE- CHARGE POWER-UP POWER APPLIED 1HY5DU561622CT SELF REFRESH AUTO REFRESH BST READ READAP READ WRITEAP PRE(PALL) Command Input Automatic Sequence 14 ...
Page 15
... Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200 cycles(tXSRD) of clock are required for locking DLL) 6. Issue Precharge commands for all banks of the device. Rev. 1.3 / Feb. 2006 Sequencing Voltage relationship to avoid latch-up After or with VDD After or with VDDQ After or with VDDQ 1HY5DU561622CT < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V 15 ...
Page 16
... CODE CODE CODE tRP tMRD tMRD EMRS Set MRS Set Precharge All Precharge All Reset DLL (with A8=H) * 200 cycle(tXSRD are required (for DLL locking) before Read Command 1HY5DU561622CT AREF MRS ACT CODE CODE CODE CODE CODE CODE tRP tRFC tMRD ...
Page 17
... Rev. 1.3 / Feb. 2006 CAS Latency A7 Test Mode 0 Normal 1 Test A8 DLL Reset Yes CAS Latency Reserved Reserved Reserved Reserved Reserved 1HY5DU561622CT Burst Length Burst Length Sequential Reserved Reserved Reserved Reserved Reserved A3 Burst Type 0 Sequential 1 Interleave Interleave Reserved Reserved Reserved Reserved Reserved ...
Page 18
... CAS LATENCY The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the Rev. 1.3 / Feb. 2006 Sequential XX0 0, 1 XX1 1, 0 X00 X01 X10 X11 000 001 010 011 100 101 110 111 1HY5DU561622CT Interleave ...
Page 19
... OUTPUT DRIVER IMPEDANCE CONTROL The HY5DU561622CT supports Full, Half strength driver and Matched impedance driver, intended for lighter load and/ or point-to-point environments. The Full drive strength for all output is specified to be SSTL_2, CLASS II. Half strength driver is to define about 50% of Full drive strength and Matched impedance driver, about 30% of Full drive strength ...
Page 20
... A10 0 1 RFU* BA0 MRS Type 0 MRS 1 EMRS * All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage. Rev. 1.3 / Feb. 2006 1HY5DU561622CT RFU* DS DLL A0 DLL enable 0 Enable 1 Diable A6 A1 Output Driver Impedance Control 0 0 Full ...
Page 21
... DDQ ± the dc value. (TA=0 to 70oC, Voltage referenced to V Symbol Min 0. 0V disabled OUT 1HY5DU561622CT Rating -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0 260 ⋅ 0V) SS Max Unit 2.5 2.625 V 2.6 2.9 V 2.8 2.9 V 2.5 2.625 V 2 ...
Page 22
... Auto Refresh I tRC=tRFC(min); All banks active DD5 Current Self Refresh CKE=<0.2V; External clock on; I DD6 Current tCK=tCK(min) Rev. 1.3 / Feb. 2006 o (TA Voltage referenced to V Test Condition 28 180 100 45 110 260 240 1HY5DU561622CT = 0V) SS Speed 180 170 160 150 150 20 100 ...
Page 23
... 0.35 IH(AC) REF V IL(AC) V 0.7 ID(AC) V 0.5*V IX(AC) DDQ of the transmitting device and must track variations in the DC level of the same. DDQ o (TA Voltage referenced to VSS = 0V 1HY5DU561622CT = 0V) SS Max Unit 0.35 V REF V + 0.6 V DDQ -0.2 0.5*V +0.2 V DDQ Value Unit V x 0.5 ...
Page 24
... DAL 2.8 7 0.45 0. 0.45 0. -0.7 0 -0.7 0.7 DQSCK t - 0.4 DQSQ t HPmin QHS t CH min t - 0.4 QHS 0.4 0.6 DQSH t 0.4 0.6 DQSL t 0.85 1.15 DQSS 0 1HY5DU561622CT 33 36 Min Max Min Max 70K 40 70K 3.3 7.0 3.6 7 0.45 0.55 0.45 0.55 ...
Page 25
... RPST WPRES t 1.5 - WPREH t 0.4 0.6 WPST MRD t 200 - XSC 1tCK t - PDEX + tIS 2tCK tPDEX_RD - + tIS t - 7.8 REFI 1HY5DU561622CT 33 36 Min Max Min Max 0.4 - 0.4 - 0.9 1.1 0.9 1.1 0.4 0.6 0.4 0 1.5 - 1.5 - 0.4 0.6 0.4 0 200 ...
Page 26
... 0.45 0. 0.45 0. -0.7 0 -0.7 0.7 DQSCK t - 0.4 DQSQ t HPmin QHS t CH min t - 0.4 QHS 0.4 0.6 DQSH t 0.4 0.6 DQSL t 0.85 1.15 DQSS 0 1HY5DU561622CT 5 6 Min Max Min Max 70K 40 70K 5.0 7.0 6.0 7.0 0.45 0.55 0.45 0.55 ...
Page 27
... WPRES t 1.5 - WPREH t 0.4 0.6 WPST MRD 200 - XSC 1tCK 1tCK t - PDEX + tIS + tIS 2tCK 2tCK tPDEX_RD - + tIS + tIS t - 7.8 REFI 1HY5DU561622CT 5 6 Max Min Max 0.4 - 0.4 - 0.9 1.1 0.9 1.1 0.4 0.6 0.4 0 1.5 - 1.5 - 0.4 0.6 0.4 0 200 ...
Page 28
... Rev. 1.3 / Feb. 2006 tRC_APCG tRFC tRAS (AUTO Precharge 40ns 16 22 40ns 18 20 40ns 17 18 40ns 14 14 40ns 11 12 40ns 1HY5DU561622CT tRCDRD tRCDWR tRP tDAL Unit tCK tCK tCK tCK tCK tCK ...
Page 29
... These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Output Rev. 1.3 / Feb. 2006 Pin CK, CK All other input-only pins DQ, DQS /2, V peak-to-peak = 0.2V O DDQ =50 Ω Zo=50 Ω V REF C =30pF L 1HY5DU561622CT Symbol Min Max Unit C 2.0 3 2.0 3 4.0 5 ...
Page 30
... Note : Package do not mold protrusion. Allowable protrusion of both sides is 0.4mm. Rev. 1.3 / Feb. 2006 BASE PLANE 22.33 (0.879) 22.12 (0.871) 0.35 (0.0138) 0.25 (0.0098) SEATING PLANE 0.15 (0.0059) 0.05 (0.0020) 1HY5DU561622CT Unit : mm(Inch) 11.94 (0.470) 11.79 (0.462) 10.26 (0.404) 10.05 (0.396 Deg. 0.597 (0.0235) 0.210 (0.0083) 0.406 (0.0160) ...