LH28F008SCT-L12 Sharp, LH28F008SCT-L12 Datasheet

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LH28F008SCT-L12

Manufacturer Part Number
LH28F008SCT-L12
Description
Flash memory 8M (1M x 8)
Manufacturer
Sharp
Datasheet

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LH28F008SCT-L12
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Part Number:
LH28F008SCT-L12
Manufacturer:
SHARP
Quantity:
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Part Number:
LH28F008SCT-L12
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LH28F008SC
FEATURES
High-Density Symmetrically-Blocked
Architecture
– Sixteen 64K Erasable Blocks
High-Performance
– 85 ns Read Access Time
Enhanced Automated Suspend Options
– Byte Write Suspend to Read
– Block Erase Suspend to Byte Write
– Block Erase Suspend to Read
Enhanced Data Protection Features
– Absolute Protection with V
– Flexible Block Locking
– Block Erase/Byte Write Lockout during
Extended Cycling Capability
– 100,000 Block Erase Cycles
– 1.6 Million Block Erase Cycles/Chip
Low Power Management
– Deep Power-Down Mode
– Automatic Power Saving Mode Decreases
Automated Byte Write and Block Erase
– Command User Interface
– Status Register
SmartVoltage Technology
– 3.3 V or 5 V V
– 3.3 V, 5 V, or 12 V V
SRAM - Compatible Write Interface
ETOX™ V Nonvolatile Flash Technology
Industry - Standard Packaging
– 42-Pin, .67 mm × 8 mm
– 40-Pin, 1.2 mm × 10 mm × 20 mm
– 44-Pin, 600-mil, SOP Package
Power Transitions
I
TSOP (Type I) Package
CC
in Static Mode
CC
PP
2
CSP Package
PP
= GND
42-PIN CSP
40-PIN TSOP
V
V
A
A
A
A
A
A
A
A
A
A
CE
RP
CC
A
A
A
A
A
A
A
B
C
D
E
PP
F
19
18
17
16
15
14
13
12
10
11
Figure 2. TSOP 40-Pin Configuration
9
8
7
6
5
4
Figure 1. CSP 42-Pin Configuration
A
A
A
A
A
A
1
5
4
6
3
2
1
10
12
13
14
15
16
17
18
19
20
11
2
3
4
5
6
7
8
9
1
DQ
DQ
A
A
A
A
2
8
7
9
0
1
0
8M (1M × 8) Flash Memory
DQ
DQ
A
A
RP
NC
3
11
10
3
2
GND
GND
V
V
V
CE
4
CC
CC
PP
DQ
DQ
DQ
A
A
A
5
12
13
14
4
6
5
RY/BY
DQ
A
A
NC
OE
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
6
15
16
7
DQ
A
A
A
TOP VIEW
TOP VIEW
NC
NC
WE
OE
RY/BY
DQ
DQ
DQ
DQ
V
GND
GND
DQ
DQ
DQ
A
WE
A
A
A
NC
NC
7
CC
0
1
2
3
17
18
19
28F008SC-20
0
7
6
5
4
3
2
1
28F008SC-1
1

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LH28F008SCT-L12 Summary of contents

Page 1

LH28F008SC FEATURES • High-Density Symmetrically-Blocked Architecture – Sixteen 64K Erasable Blocks • High-Performance – Read Access Time • Enhanced Automated Suspend Options – Byte Write Suspend to Read – Block Erase Suspend to Byte Write – Block Erase ...

Page 2

... GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. The LH28F008SC is manufactured on SHARP’s 0.4 µm ETOX™ V process technology. It comes in in- dustry-standard packages: the 40-pin TSOP , ideal for board constrained applications, and the rugged 44-pin SOP ...

Page 3

Flash Memory INPUT BUFFER Y-DECODER ADDRESS LATCH X-DECODER ADDRESS COUNTER Internal V and V detection Circuitry automati cally configures the device for optimized read and write operations. A Command ...

Page 4

LH28F008SC PIN DESCRIPTION SYMBOL TYPE ADDRESS INPUTS: Inputs for addresses during read and write operations INPUT 0 19 Addresses are internally latched during a write cycle. DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs ...

Page 5

Flash Memory     »     » The output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking ...

Page 6

... If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing sta- tus information instead of array data. SHARP’s flash     »     » and OE ...

Page 7

Flash Memory FFFFF RESERVED FOR F0004 FUTURE IMPLEMENTATION F0003 F0002 BLOCK 15 LOCK CONFIGURATION CODE F0001 RESERVED FOR FUTURE IMPLEMENTATION F0000 (BLOCKS 2 THROUGH 14) 1FFFF RESERVED FOR 10004 FUTURE IMPLEMENTATION 10003 BLOCK 1 LOCK CONFIGURATION ...

Page 8

LH28F008SC BUS OPERATIONS » MODE RP Read Output Disable Standby Deep Power Down V IL Read Identifier Codes Write V ...

Page 9

... If the master lock-bit is set, RP must block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP 9. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. FIRST BUS CYCLE 1 ...

Page 10

LH28F008SC Read Identifier Codes Command The identifier code operation is initiated by writing the Read Identifier Codes command. Following the com- mand write, read cycles from addresses shown in Fig- ure 5 retrieve the manufacturer, device, block lock configuration and ...

Page 11

Flash Memory Byte Write Command Byte write is executed by a two-cycle command sequence. Byte write setup (standard 40H or alternate 10H) is written, followed by a second write that speci- fies the address and data ...

Page 12

LH28F008SC Set Block and Master Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a mas- ter lock-bit. The block lock-bits gate program and erase operations while the master lock-bit gates ...

Page 13

Flash Memory Write Protection Alternatives MASTER BLOCK OPERATION LOCK-BIT LOCK-BIT 0 Block Erase or X Byte Write Set Block Lock Bit 1 X Set Master X X Lock-Bit 0 X Clear Block Lock-Bits ...

Page 14

LH28F008SC START WRITE 20H BLOCK ADDRESS WRITE D0H BLOCK ADDRESS READ STATUS REGISTER SUSPEND BLOCK NO ERASE LOOP SUSPEND 0 SR.7 = BLOCK ERASE? 1 FULL STATUS CHECK IF DESIRED BLOCK ERASE COMPLETED FULL STATUS CHECK PROCEDURE STATUS REGISTER DATA ...

Page 15

Flash Memory START WRITE 40H ADDRESS WRITE BYTE DATA AND ADDRESS READ STATUS REGISTER ERASE SUSPEND NO WRITE LOOP SUSPEND 0 SR.7 = BYTE WRITE? 1 FULL STATUS CHECK IF DESIRED BYTE WRITE COMPLETED FULL STATUS ...

Page 16

LH28F008SC START WRITE B0H READ STATUS REGISTER 0 SR SR.6 = ERASE COMPLETED 1 READ or Read Byte Write BYTE WRITE ? Read Byte Array Data Write Loop NO DONE ? YES WRITE D0H BLOCK READ ARRAY ...

Page 17

Flash Memory START WRITE B0H READ STATUS REGISTER 0 SR BYTE WRITE SR.2 = COMPLETED 1 WRITE FFH READ ARRAY DATA DONE NO READING YES WRITE D0H WRITE FFH BYTE READ ARRAY DATA ...

Page 18

LH28F008SC START WRITE 60H BLOCK/DEVICE ADDRESS WRITE 01H/F1H BLOCK/DEVICE ADDRESS READ STATUS REGISTER 0 SR FULL STATUS CHECK IF DESIRED SET LOCK-BIT COMPLETED FULL STATUS CHECK PROCEDURE READ STATUS REGISTER DATA (see above RANGE PP SR.3 ...

Page 19

Flash Memory START WRITE 60H WRITE D0H READ STATUS REGISTER 0 SR FULL STATUS CHECK IF DESIRED CLEAR BLOCK LOCK-BITS COMPLETE FULL STATUS CHECK PROCEDURE READ STATUS REGISTER DATA (see above RANGE ...

Page 20

... LH28F008SC DESIGN CONSIDERATIONS Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accom- modate multiple memory connections. Three-line control provides for: • Lowest possible memory power dissipation • Complete assurance that data bus contention will not occur ...

Page 21

... Do not finalize a design with this information. Revised informa- tion will be published when the product is available. Veryify with your local SHARP sales office that you have the latest datasheet before finalizing a design. * WARNING: Stressing the device beyond the “Abso- lute Maximum Ratings” ...

Page 22

LH28F008SC Capacitance T = +25° MHz A SYMBOL PARAMETER TYP. C Input Capacitance IN C Output Capacitance OUT NOTE: 1. Sampled, not 100% tested. AC INPUT/OUTPUT TEST CONDITIONS 3.0 INPUT 1.5 TEST POINTS 0.0 NOTE: AC test ...

Page 23

Flash Memory DC CHARACTERISTICS V SYM. PARAMETER TYP. I Input Load Current LI I Output Leakage Current Standby Current CCS CC V Deep Power-Down CC I CCD Current I V Read Current CCR ...

Page 24

... HH NOTES: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact SHARP’s Application Support Hotline or your local sales office for information about typical specifications and I are specified with the device de-selected. If read or byte written while in erase suspend mode, the device’s current ...

Page 25

Flash Memory AC CHARACTERISTICS - Read Only Operations V = 3.3 V ± 0 0°C to +70° SYMBOL PARAMETER t Read Cycle Time AVAV t Address to Output Delay AVQV » ...

Page 26

LH28F008SC V IH ADDRESSES ( ( ( ( HIGH-Z DATA (D/ ...

Page 27

Flash Memory AC CHARACTERISTICS - Write Operations V = 3.3 V ± 0 0°C to +70° SYMBOL PARAMETER t Write Cycle Time AVAV t RP » High Recovery to WE Going ...

Page 28

LH28F008SC AC CHARACTERISTICS - Write Operations ± 0 ± 0. SYMBOL PARAMETER t Write Cycle Time AVAV » RP High Recovery PHWL Going Low » ...

Page 29

Flash Memory V IH ADDRESSES ( ( ( ( DATA (D/ RY/BY (R) ...

Page 30

LH28F008SC ALTERNATIVE CE     » - Controlled Writes V = 3.3 V ± 0 0°C to +70° SYMBOL PARAMETER t Write Cycle Time AVAV » High Recovery to CE PHEL t » ...

Page 31

Flash Memory ALTERNATIVE CE     » - Controlled Writes ± 0 ± 0. 0°C to +70°C CC SYMBOL PARAMETER t Write Cycle Time AVAV » ...

Page 32

LH28F008SC V IH ADDRESSES ( ( ( ( DATA (D/ RY/BY ( ...

Page 33

Flash Memory RESET OPERATIONS V IH RY/ RY/ Reset During Block Erase, Byte Write, or ...

Page 34

LH28F008SC BLOCK ERASE, BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE V = 3.3 V ± 0 0°C to +70° SYM. PARAMETER TYP WHQV Byte Write Time 1 t EHQV Block Write Time 2 t ...

Page 35

Flash Memory 44SOP (SOP044-P-0600) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012 28.40 [1.118] 28.00 [1.102] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 23 13.40 [0.528] 16.40 [0.646] 13.00 [0.512] 15.60 [0.614] SEE 22 ...

Page 36

LH28F008SC 42CSP (CSP042-P-0808) INDEX 8.20 [0.323] 7.80 [0.307] 0.10 [0.004] 0.10 [0.004] 1.0 [1.039] 1.0 [1.039] TYP. TYP. MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 36 0.40 [0.016] (See Detail) DETAIL 0.30 [0.012] 0.48 [0.019] 0.42 [0.017] 0.15 [0.006] ...

Page 37

... DIMENSIONS IN MM [INCHES] MINIMUM LIMIT ORDERING INFORMATION LH28F008SC X -85 Device Type Package Speed Example: LH28F008SCT-85 ( Flash Memory, 85 ns, 40-pin TSOP) 18.60 [0.732] 18.20 [0.717] 19.30 [0.760] 18.70 [0.736] 20.30 [0.799] 19.70 [0.776] 85 Access Time (ns) T 40-pin, 1 TSOP (Type I) (TSOP040-P-1020) N 44-pin, 600-mil SOP (SOP044-P-0600 42-pin, ...

Page 38

... Product which fails during the warranty period because of such defect (if Customer promptly reported the failure to SHARP in writing) or, (ii) if SHARP is unable to repair or replace, SHARP will refund the purchase price of the Product upon its return to SHARP . This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than SHARP ...

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