LH28F320BFE-PTTL60 Sharp, LH28F320BFE-PTTL60 Datasheet
LH28F320BFE-PTTL60
Related parts for LH28F320BFE-PTTL60
LH28F320BFE-PTTL60 Summary of contents
Page 1
... Flash Memory LH28F320BFE-PTTL60 Date Dec. 10. 2002 ...
Page 2
Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe ...
Page 3
TSOP Pinout................................................. 3 Pin Descriptions.......................................................... 4 Simultaneous Operation Modes Allowed with Four Planes .................................. 5 Memory Map .............................................................. 6 Identifier Codes and OTP Address for Read Operation ............................................. 7 Identifier Codes and OTP Address for Read Operation on Partition ...
Page 4
... Fast program capability is provided through the use of high speed Page Buffer Program. Special OTP (One Time Program) block provides an area to store permanent code such as a unique number. * ETOX is a trademark of Intel Corporation. LHF32FB1 LH28F320BFE-PTTL60 32Mbit (2Mbit 16) Flexible Blocking Architecture • Eight 4K-word Parameter Blocks • ...
Page 5
WE# 11 RST WP#/ACC 14 RY/BY# 15 ...
Page 6
Symbol Type A -A ADDRESS INPUTS: Inputs for addresses. 32M: A INPUT 0 20 DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User Interface) write cycles, outputs data during memory array, status register, query code, INPUT/ DQ -DQ identifier ...
Page 7
Table 2. Simultaneous Operation Modes Allowed with Four Planes IF ONE Read Read PARTITION IS: Array ID/OTP Read Array X X Read ID/OTP X X Read Status X X Read Query X X Word Program X X Page Buffer X ...
Page 8
BLOCK NUMBER ADDRESS RANGE 70 4K-WORD 1FF000H - 1FFFFFH 69 4K-WORD 1FE000H - 1FEFFFH 68 4K-WORD 1FD000H - 1FDFFFH 67 4K-WORD 1FC000H - 1FCFFFH 66 4K-WORD 1FB000H - 1FBFFFH 65 4K-WORD 1FA000H - 1FAFFFH 64 4K-WORD 1F9000H - 1F9FFFH 63 ...
Page 9
Table 3. Identifier Codes and OTP Address for Read Operation Manufacturer Code Manufacturer Code Device Code Top Parameter Device Code Block Lock Configuration Block is Unlocked Code Block is Locked Block is not Locked-Down Block is Locked-Down Device Configuration Code ...
Page 10
LHF32FB1 [ 000088H Customer Programmable Area 000085H 000084H Factory Programmed Area 000081H Reserved for Future Implementation 000080H (DQ -DQ 15 Customer Programmable Area Lock Bit (DQ Factory Programmed Area Lock Bit (DQ Figure 3. OTP Block ...
Page 11
Mode Notes RST# Read Array Output Disable V IH Standby V IH Reset Read Identifier Codes/OTP V Read Query 6,7 IH Write 4,5 NOTES: 1. See DC Characteristics for ...
Page 12
Command Read Array Read Identifier Codes/OTP Read Query Read Status Register Clear Status Register Block Erase Full Chip Erase Program Page Buffer Program Block Erase and (Page Buffer) Program Suspend Block Erase and (Page Buffer) Program Resume Set Block Lock ...
Page 13
... Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when WP#/ACC is V When WP#/ACC lock-down bit is disabled and the selected block is unlocked regardless of lock-down IH configuration. 11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. LHF32FB1 11 . ...
Page 14
Table 7. Functions of Block Lock Current State (1) State WP#/ACC DQ 1 [000 ( [001] [011 [100 ( [101] ( [110] [111 NOTES ...
Page 15
Table 9. Block Locking State Transitions upon WP#/ACC Transition Current State Previous State State WP#/ACC - [000] - [001] (2) [011] [110] (2) Other than [110] - [100] - [101] - [110] - [111] NOTES: 1. "WP#/ACC=0 1" means that ...
Page 16
WSMS BESS BEFCES 7 6 SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS ...
Page 17
SMS XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS Page Buffer Program available 0 = Page Buffer Program not available XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS ...
Page 18
PCR.15-11 = RESERVED FOR FUTURE ENHANCEMENTS (R) PCR.10-8 = PARTITION CONFIGURATION (PC2-0) 000 = No partitioning. Dual Work is not allowed. 001 = Plane1-3 are merged into one partition. (default in a ...
Page 19
Electrical Specifications 1.1 Absolute Maximum Ratings Operating Temperature During Read, Erase and Program ...... +70 C Storage Temperature During under Bias............................... - +80 C During non Bias................................ - +125 C Voltage On ...
Page 20
Capacitance ( f=1MHz) A Parameter Input Capacitance WP#/ACC Input Capacitance Output Capacitance NOTE: 1. Sampled, not 100% tested. 1.2.2 AC Input/Output Test Conditions V CC INPUT 0.0 AC test inputs are driven at V Input ...
Page 21
DC Characteristics Symbol Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Automatic Power Savings Current CCAS Reset Power-Down Current CCD CC Average V Read CC ...
Page 22
Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH WP#/ACC during Block Erase, Full V Chip Erase, (Page Buffer) Program or ACCH OTP Program Operations V V ...
Page 23
AC Characteristics - Read-Only Operations Symbol t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t Page Address Access Time APA t OE# to Output Delay GLQV t RST# High to ...
Page 24
(A) 20 EHEL V IH CE# ( OE# ( (W) WE (D/Q) 15 (P) RST# V ...
Page 25
(A) 20 (A) 2 (E) CE OE# ( WE# ( High (D/Q) 15-0 V ...
Page 26
(A) 20 (A) 2 (E) CE OE# ( WE# ( GLQX t ELQX V High Z OH ...
Page 27
AC Characteristics - Write Operations Symbol t Write Cycle Time AVAV RST# High Recovery to WE# (CE#) Going Low PHWL PHEL CE# (WE#) Setup to WE# (CE#) Going Low ELWL WLEL t (t ...
Page 28
NOTE (A) 20 (E) CE ELWL WLEL V IH OE# ( PHWL PHEL V IH WE# ( (D/Q) 15-0 ...
Page 29
Reset Operations V IH RST# ( High (D/Q) 15 RST# ( High (D/Q) 15 (min GND V ...
Page 30
Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance Symbol Parameter 4K-Word Parameter Block t WPB Program Time 32K-Word Main Block t WMB Program Time t / WHQV1 Word Program Time t EHQV1 t / WHOV1 ...
Page 31
... Related Document Information Document No. FUM00701 NOTE: 1. International customers should contact their local SHARP or distribution sales offices. LHF32FB1 (1) Document Name LH28F320BF series Appendix 29 Rev. 2.44 ...
Page 32
LH28F320BFXX-XXXXXX Flash MEMORY ERRATA 1. AC Characteristics PROBLEM The table below summarizes the AC characteristics. AC Characteristics - Write Operations Page Symbol t 25 Write Cycle Time AVAV WE# (CE#) Pulse Width WLWH ELEH t (t ...
Page 33
A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
Page 34
A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
Page 35
A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
Page 36
... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...
Page 37
A-3 STATUS REGISTER READ OPERATIONS If AC timing for reading the status register described in specifications is not satisfied, a system processor can check the status register bit SR.15 instead of SR.7 to determine when the erase or program operation ...