DA28F016SA-100 Intel Corporation, DA28F016SA-100 Datasheet

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DA28F016SA-100

Manufacturer Part Number
DA28F016SA-100
Description
Manufacturer
Intel Corporation
Datasheet

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Part Number:
DA28F016SA-100
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INTEL
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DA28F016SA-100-5.0V
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XILINX
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Intel’s 28F016SA 16-Mbit FlashFile™ memory is a revolutionary architecture which is the ideal choice for
designing embedded direct-execute code and mass storage data/file flash memory systems. With innovative
capabilities, low-power, extended temperature operation and high read/program performance, the 28F016SA
enables the design of truly mobile, high-performance communications and computing products.
The 28F016SA is the highest density, highest performance nonvolatile read/program solution for solid-state
storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F008SA 8-Mbit
FlashFile memory), extended cycling, extended temperature operation, flexible V
performance and selective block locking provide highly flexible memory components suitable for Resident
Flash Arrays, high-density memory cards and PCMCIA-ATA flash drives. The 28F016SA dual read voltage
enables the design of memory cards which can be interchangeably read/written in 3.3V and 5.0V systems. Its
x8/x16 architecture allows optimization of the memory-to-processor interface. Its high read performance and
flexible block locking enable both storage and execution of operating systems and application software.
Manufactured on Intel’s 0.6 µm ETOX IV process technology, the 28F016SA is the most cost-effective,
highest density monolithic 3.3V FlashFile memory.
November 1996
User-Selectable 3.3V or 5V V
User-Configurable x8 or x16 Operation
70 ns Maximum Access Time
28.6 MB/sec Burst Write Transfer Rate
1 Million Typical Erase Cycles per
Block
56-Lead, 1.2 mm x 14 mm x 20 mm
TSOP Package
56-Lead, 1.8 mm x 16 mm x 23.7 mm
SSOP Package
Includes Commercial and Extended Temperature Specifications
(1 MBIT X 16, 2 MBIT X 8)
FlashFile™ MEMORY
28F016SA 16-MBIT
CC
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Revolutionary Architecture
1 mA Typical I
1 µA Typical Deep Power-Down
32 Independently Lockable Blocks
State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology
Pipelined Command Execution
Program during Erase
Command Superset of Intel
28F008SA
CC
in Static Mode
CC
, fast program and read
Order Number: 290489-004

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DA28F016SA-100 Summary of contents

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E 28F016SA 16-MBIT (1 MBIT X 16, 2 MBIT X 8) FlashFile™ MEMORY Includes Commercial and Extended Temperature Specifications n User-Selectable 3. User-Configurable x8 or x16 Operation Maximum Access Time n 28.6 ...

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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 COPYRIGHT © INTEL CORPORATION, 1996 CG-041493 ...

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E 1.0 INTRODUCTION ............................................. 5 1.1 Product Overview ........................................ 5 2.0 DEVICE PINOUT............................................. 6 2.1 Lead Descriptions ........................................ 8 3.0 MEMORY MAPS ........................................... 12 3.1 Extended Status Register Memory Map..... 13 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS............. 14 ...

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REVISION HISTORY Number -001 Original Version -002 — Added 56-Lead SSOP Package — Separated AC Reading Timing Specs t Reads — Modified Device Nomenclature — Added Ordering Information — Added Page Buffer Typical Program Performance numbers — Added Typical ...

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E 1.0 INTRODUCTION The documentation of the Intel 28F016SA memory device includes this datasheet, a detailed user’s manual, and a number of application notes, all of which are referenced at the end of this datasheet. The datasheet is intended to ...

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The 28F016SA can also perform program operations to one block of memory while performing erase of another block. The 28F016SA provides ...

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E DQ 8-15 Output Buffer Input Buffer Y Decoder Address Queue Latches X Decoder Address Counter Figure 1. 28F016SA Block Diagram Architectural Evolution Includes Page Buffers, Queue Registers and Extended Status Registers DQ 0-7 Output Input Input Buffer Buffer Buffer ...

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Lead Descriptions Symbol Type A INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when the 0 device mode. This address is latched in x8 data programs. Not used in x16 mode (i.e., the A ...

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E 2.1 Lead Descriptions (Continued) Symbol Type RY/BY# OPEN DRAIN READY/BUSY: Indicates status of the internal WSM. When low, it OUTPUT indicates that the WSM is busy performing an operation. RY/BY# high indicates that the WSM is ready for new ...

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...

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... E 28F016SV 3/5# 3/ GND GND RY/BY# RY/BY# 20 OE# OE# 21 WE# WE# 22 WP# WP Figure 3. SSOP Pinout Configuration DA28F016SA 45 56-LEAD SSOP 44 STANDARD PINOUT TOP VIEW 28F016SA 28F016SV RP# RP GND GND BYTE# BYTE GND GND 0489_17 11 ...

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MEMORY MAPS A [20-0] 1FFFFF 1F0000 1EFFFF 1E0000 1DFFFF 1D0000 1CFFFF 1C0000 1BFFFF 1B0000 1AFFFF 1A0000 19FFFF 190000 18FFFF 180000 17FFFF 170000 16FFFF 160000 15FFFF 150000 14FFFF 140000 13FFFF 130000 12FFFF 120000 11FFFF 110000 10FFFF 100000 0FFFFF 0F0000 ...

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E 3.1 Extended Status Register Memory Map x8 MODE A[20-0] 1F0006H RESERVED 1F0005H GSR 1F0004H RESERVED 1F0003H BSR 31 1F0002H RESERVED 1F0001H RESERVED 1F0000H . . . 010002H RESERVED 000006H RESERVED 000005H GSR 000004H RESERVED 000003H BSR 0 000002H RESERVED ...

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BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS 4.1 Bus Operations for Word-Wide Mode (BYTE Mode Notes RP# Read 1,2 Output Disable 1,6 Standby 1,6 Deep Power-Down 1 Manufacturer ...

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E 4.3 28F008SA–Compatible Mode Command Bus Definitions Command Notes Read Array Intelligent Identifier Read Compatible Status Register Clear Status Register Word/Byte Program Alternate Word/Byte Program Block Erase/Confirm Erase Suspend/Resume ADDRESS A = Array Address BA = Block Address IA = ...

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Enhancement Command Bus Definitions Command Mode Notes Oper Read Extended 1 Write Status Register Page Buffer Swap 7 Write Read Page Buffer Write Single Load to Page Write Buffer Sequential Load to x8 4,6,10 Write Page Buffer ...

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E NOTES can be the GSR address or any BSR address. See Figures 5 and 6 for Extended Status Register Memory Maps. 2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must ...

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Compatible Status Register WSMS ESS CSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy CSR.6 = ERASE-SUSPEND STATUS 1 = Erase Suspended 0 = Erase In Progress/Completed CSR.5 = ERASE STATUS ...

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E 4.6 Global Status Register WSMS OSS DOS GSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy GSR.6 = OPERATION SUSPEND STATUS 1 = Operation Suspended 0 = Operation in Progress/Completed GSR.5 = DEVICE ...

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Block Status Register BS BLS BOS BSR.7 = BLOCK STATUS 1 = Ready 0 = Busy BSR.6 = BLOCK-LOCK STATUS 1 = Block Unlocked for Program/Erase 0 = Block Locked for Program/Erase BSR.5 = BLOCK ...

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E 5.0 ELECTRICAL SPECIFICATIONS 5.1 Absolute Maximum Ratings* Temperature under Bias .....................0°C to +80°C Storage Temperature....................–65°C to +125° 3.3V ± 10% Systems CC Sym Parameter T Operating Temperature, Commercial with Respect to GND CC CC ...

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Capacitance For a 3.3V System: Symbol Parameter Capacitance Looking into Address/Control Pin Capacitance Looking into an C OUT Output Pin Load Capacitance Driven by C LOAD Outputs for Timing Specifications Equivalent Testing Load Circuit For ...

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E 5.3 Timing Nomenclature All 3.3V system timings are measured from where signals cross 1.5V. For 5.0V systems use the standard JEDEC cross point definitions. Each timing parameter consists of five characters. Some common examples are defined below ...

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INPUT 0.8 0.45 AC test inputs are driven at V (2.4 VTTL) for a Logic “1” and V OH (2.0 VTTL) and V (0.8 VTTL). Output timing ends Figure 7. Transient Input/Output Reference Waveform ...

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E 2 Transmission Line From Output under Test Total Capacitance = 100 pF Figure 9. Transient Equivalent Testing Load Circuit (V 2 From Output under Test Total Capacitance = 50 pF Figure 10. Transient ...

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DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE 3.3V ±10 +70 C, – + 3/5# = Pin Set High for 3.3V Operations Temp Sym Parameter Notes I Input ...

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E 5.4 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE (Continued 3.3V ±10 +70 C, – + 3/5# = Pin Set High for 3.3V Operations Temp Sym Parameter Notes I ...

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DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE (Continued 3.3V ± 10 +70 C, – + 3/5# = Pin Set High for 3.3V Operations Temp Sym Parameter Notes ...

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E 5.5 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE V = 5.0V ± 10%, 5.0V ± 5 +70 C, – + 3/5# Pin Set Low for 5V Operations Temp Sym Parameter ...

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DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE (Continued 5.0V ± 10%, 5.0V ± 5 +70 C, – + 3/5# Pin Set Low for 5V Operations Temp Sym ...

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E 5.5 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE (Continued 5.0V ± 10%, 5.0V ± 5%, + 3/5# Pin Set Low for 5V Operations Temp Sym Parameter ...

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AC Characteristics–Read Only Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 3.3V ± 10 +70 C, – + Temp Speed Sym Parameter V CC Load Notes t Read Cycle ...

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E 5.6 AC Characteristics–Read Only Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 5.0V ± 10%, 5.0V ± 5 +70 C. – + Temp Speed Sym Parameter V CC Load Notes ...

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For Extended Status Register Reads Temp Load Versions V ± ± 10% CC Sym Parameter Notes t Address 3,4 AVEL Setup to CE# Going Low t Address 3,4 AVGL Setup to OE# Going Low NOTES: ...

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ADDRESSES (A) ADDRESSES STABLE (1) CEx# ( AVEL AVGL OE# ( WE# ( GLQX ELQX HIGH Z ...

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V IH ADDRESSES ( (1) CEx #( AVFL AVEL OE# ( ELFL t AVGL V IH BYTE# ( ...

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E 5.7 Power-Up and Reset Timings: COMMERCIAL/EXTENDED TEMPERATURE V Power-Up CC RP# t YHPH (P) 3/5# (Y) 3. (3V,5V PHEL3 Address (A) t AVQV Data Valid 3.3V Outputs (Q) t PHQV Figure 14. ...

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AC Characteristics for WE#–Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 3.3V ± 10 +70 C, – + Sym Parameter t Write Cycle Time AVAV t ...

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E 5.8 AC Characteristics for WE#–Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 5.0V ±10%, 5.0V ± 5 +70 C, – + Temp Versions V ± ...

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AC Characteristics for WE#–Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 5.0V ±10%, 5.0V ± 5 +70 C, – + Temp Versions V ± ...

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E NOTES: CE# is defined as the latter going low or the first Read timings during data program and block erase are the same as for normal read. 2. ...

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AC Characteristics for CE#–Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 3.3V ±10 + Sym Parameter t Write Cycle Time AVAV t V ...

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E 5.9 AC Characteristics for CE#–Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 5.0 to 10% , 5.0 ± 5 0°C to +70 C, –40° Temp Versions V ± ...

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AC Characteristics for CE#–Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 5.0 to 10%, 5.0V ± 5 +70 C, – + Temp Versions V ± 5% ...

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E WRITE VALID ADDRESS DEEP WRITE DATA-WRITE OR & DATA (DATA-WRITE) OR POWER-DOWN ERASE SETUP COMMAND ERASE CONFIRM COMMAND V IH ADDRESSES ( NOTE AVAV AVEH V IH ADDRESSES ( ...

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AC Characteristics for Page Buffer Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 3.3V ± 10 +70 C, – + Sym Parameter t Write Cycle Time AVAV t ...

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E 5.10 AC Characteristics for Page Buffer Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 5.0V ± 10%, 5.0V ± 5 +70 C, – + Temp Sym Parameter Speed V ...

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V IH CEx#( ELWL V IH WE# ( AVWL ADDRESSES ( HIGH Z DATA (D/ Figure 17. Page Buffer Write Timing Waveforms (Loading Data to ...

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E 5.11 Erase and Word/Byte Write Performance, Cycling Performance and (3) Suspend Latency V = 3.3V ± 10 12.0V ± 0.6V Sym Parameter Page Buffer Byte Write Time Page Buffer Word Write Time t 1 ...

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DERATING CURVES Figure 18. I vs. Frequency (V = 5.5V) for x16 Operation Figure 19. I during Block Erase CC 50 290489-16.eps Figure 20. I vs. Frequency ( x16 Operation 290489-18.eps Figure ...

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E Figure 22. Access Time (t Figure 23. I during Word Write Operation PP ) vs. Output Loading ACC 290489-25.eps Figure 24. I during Page Buffer Write PP Operation 28F016SA 290489-24.eps 290489-26 51 ...

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MECHANICAL SPECIFICATIONS FOR TSOP Figure 25. Mechanical Specifications of the 28F016SA 56-Lead TSOP Type 1 Package Family: Thin Small Outline Package Symbol Minimum 0.965 2 b 0.100 c 0.115 D 18. ...

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E 8.0 MECHANICAL SPECIFICATIONS FOR SSOP Figure 26. Mechanical Specifications of the 56-Lead SSOP Package Family: Shrink Small Outline Package Symbol Minimum A A1 0.47 A2 1.18 B 0.25 C 0.13 D 23.40 E 13.10 ...

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... Order Code Load 1 E28F016SA-070 E28F016SA-120 2 E28F016SA-100 E28F016SA-150 3 DA28F016SA-070 DA28F016SA-120 4 DA28F016SA-100 DA28F016SA-150 5 DT28F016SA-100 DT28F016SA-150 54 APPENDIX ACCESS SPEED 70 ns 100 ns 100 ns Valid Combinations = 3.3V ± 10 5.0V ± 10%, CC 100 pF Load E28F016SA-080 E28F016SA-100 DA28F016SA-080 DA28F016SA-100 DT28F016SA-150 E 0 0489_18 V = 5.0V ± 5 Load E28F016SA-070 DA28F016SA-070 DT28F016SA-150 ...

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E ADDITIONAL INFORMATION Order Number 297372 16-Mbit Flash Product Family User’s Manual 290490 DD28F032SA 32-Mbit FlashFile™ Memory Datasheet 290528 28F016SV FlashFile™ Memory Datasheet 290429 28F008SA 8-Mbit FlashFile™ Memory Datasheet 292092 AP-357 Power Supply Solutions for Flash Memory 292123 AP-374 Flash ...

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