MT90820AP Zarlink Semiconductor, MT90820AP Datasheet

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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2000-2005, Zarlink Semiconductor Inc. All Rights Reserved. CMOS ST-BUS MT90820AP MT90820AL MT90820APR MT90820AL1 MT90820AP1 MT90820APR1 Applications • Medium and large switching platforms • CTI application • Voice/data multiplexer • ...

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... Per stream input delay control is particularly useful for managing large multi-chip switches that transport both voice channel and concatenated data channels. In addition, input stream can be individually calibrated for input frame offset using a dedicated pin. MT90820 2 Zarlink Semiconductor Inc. Data Sheet ...

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... STi4 86 STi5 STi6 88 STi7 STi8 90 STi9 STi10 100 PIN MQFP STi11 92 STi12 94 STi13 STi14 96 STi15 F0i 98 FE/HCLK 99 VSS CLK Figure 2 - Pin Connections Zarlink Semiconductor Inc. MT90820 CSTo DTA 73 D15 D14 71 D13 D12 69 D11 D10 PIN PLCC 65 VSS VDD 63 AD7 AD6 61 AD5 ...

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... Internal Connection (Input): Connect to V low for the MT90820 to function normally and to comply with IEEE 1149 (JTAG) boundary scan requirements. This pin is pulled low internally when not driven. MT90820 Description for normal operation. This pin must Zarlink Semiconductor Inc. Data Sheet ...

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... Control Output (Output). This is a 4.096, 8.192 or 16.384 Mb/s output containing 512, 1024 or 2048 bits per frame respectively. The level of each bit is determined by the CSTo bit in the connection memory. See External Drive Control Section. MT90820 Description 5 Zarlink Semiconductor Inc. Data Sheet ...

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... The sequential addressing of the data memory is performed by an internal counter, which is reset by the input 8 kHz frame pulse (F0i) to mark the frame boundaries of the incoming serial data streams. MT90820 Description 6 Zarlink Semiconductor Inc. Data Sheet ...

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... CLK, three quarters of the way into the bit cell. In GCI format, every second rising edge of the master clock marks the bit boundary and data is clocked in on the falling edge of CLK at three quarters of the way into the bit cell, see Figure 12. MT90820 7 Zarlink Semiconductor Inc. Data Sheet ...

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... Serial Interface MT90820 Master Clock Matrix Channel Required Data Rate (MHz) 2 Mb/s 4.096 4 Mb/s 8.192 8 Mb/s 16.384 Table 1 - Switching Configuration 8 Zarlink Semiconductor Inc. Data Sheet Capacity 512 x 512 1,024 x 1,024 2,048 x 2,048 ...

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... The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on the per-channel basis. For voice application, select variable throughput delay to ensure minimum MT90820 9 Zarlink Semiconductor Inc. Data Sheet ...

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... Table 2 - Variable Throughput Delay Value Delay for Constant Throughput Delay Mode 10 Zarlink Semiconductor Inc. Data Sheet m > n+2 m-n time-slots m-n time-slots m-n time-slots (m - output channel number input channel number ( time-slots ...

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... CSTo pin and are synchronous with the data rates on the other ST-BUS streams. The CSTo bit is output one channel before the corresponding channel on the ST-BUS. For example Mb/s mode, the contents of the CSTo bit in position 0 (STo0, CH0) of the connection memory is output on the first clock MT90820 11 Zarlink Semiconductor Inc. Data Sheet ...

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... A5 A4 (Note MT90820 Control Register Interface Mode Selection Register, IMS Frame Alignment Register, FAR Frame Input Offset Register 0, FOR0 Frame Input Offset Register 1, FOR1 Frame Input Offset Register 2, FOR2 Frame Input Offset Register 3, FOR3 Zarlink Semiconductor Inc. Data Sheet Location Note 2) ( ...

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... ODE pin OSB bit in IMS register Don’t Care Don’t Care 0000 . Description 13 Zarlink Semiconductor Inc. Data Sheet Location Note 126 Ch 127 Note 4) ( ST-BUS Output Driver Status Per Channel High Impedance High Impedance Enable Enable Enable MBP MS STA3 STA2 STA1 ...

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... When BPE = 1, the other bits in the IMS register must not be changed for two frames to ensure proper operation. MT90820 , MBP Description Table 6 - Control (CR) Register Bits , BPD BPD BPD BPD BPD Description 14 Zarlink Semiconductor Inc. Data Sheet STA3 STA2 STA1 STA0 Valid Address Lines A4, A3, A2, A1, A0 A5, A4, A3, A2, A1, A0 A6, A5, A4 A3, A2, A1 BPE OSB SFE DR1 DR0 0 ...

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... Description Data Rate Selected 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s Reserved , FD10 FD9 FD8 FD7 FD6 FD5 Description 15 Zarlink Semiconductor Inc. Data Sheet BPE OSB SFE DR1 DR0 Master Clock Required 4.096 MHz 8.192 MHz 16.384 MHz Reserved FD4 FD3 FD2 ...

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... CLK Offset Value 0 FE Input Figure 3 - Example for Frame Alignment Measurement MT90820 , FD10 FD9 FD8 FD7 FD6 FD5 Description (FD[10: (FD11 = 0, sample at CLK low phase (FD[10: (FD11 = 1, sample at CLK high phase) 16 Zarlink Semiconductor Inc. Data Sheet FD4 FD3 FD2 FD1 FD0 ...

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... DLEn =0, if clock falling edge is at the 3/4 point of the bit cell. DLEn =1, if when clock rising edge is at the 3/4 of the bit cell. Measurement Result from Frame Delay Bits FD11 FD2 FD1 FD0 Zarlink Semiconductor Inc. Data Sheet DLE1 OF02 OF01 OF00 DLE0 ...

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... FD1 FD0 Bit 7 Bit 7 Bit 7 denotes the 3/4 point of the bit cell Bit 0 Bit 0 Bit 0 denotes the 3/4 point of the bit cell 18 Zarlink Semiconductor Inc. Data Sheet Corresponding Offset Bits OFn2 OFn1 OFn0 DLEn offset=0, DLE=0 offset=1, DLE=0 offset=0, DLE=1 offset=1, DLE=1 ...

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... Source Channel Address Bits. The binary value is the number of the channel for the source of the connection. Table 13 - Connection Memory Bits CAB Bits Used to Determine the Source Channel of the Connection CAB4 to CAB0 (32 channel/input stream) CAB5 to CAB0 (64 channel/input stream) CAB6 to CAB0 (128 channel/input stream) 19 Zarlink Semiconductor Inc. Data Sheet ...

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... The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO. The MT90820 boundary scan register contains 118 bits. Bit 0 in Table 15 Boundary Scan Register is the first bit clocked out. All tristate enable bits are active high. MT90820 20 Zarlink Semiconductor Inc. Data Sheet ...

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... D14 23 24 D13 26 27 D12 29 30 D11 32 33 D10 AD7 44 45 AD6 47 48 AD5 50 51 AD4 53 54 AD3 56 57 AD2 59 60 AD1 62 63 AD0 AS/ALE CS R DS/ WFPS RESET Table 15 - Boundary Scan Register Bits 21 Zarlink Semiconductor Inc. Data Sheet Input Scan Cell ...

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... STi1 STi0 STo15 102 103 STo14 104 105 STo13 106 107 STo12 108 109 STo11 110 111 STo10 112 113 STo9 114 115 STo8 116 117 Table 15 - Boundary Scan Register Bits 22 Zarlink Semiconductor Inc. Data Sheet Input Scan Cell 100 101 ...

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... MT90820 #3 MT90820 #4 MT90820 Frame Alignment Evaluation circuit External FE CLK FP Mux input 23 Zarlink Semiconductor Inc. Data Sheet 16 Streams OUT 16 Streams Bit Rate Size of (IN/OUT) Switch Matrix 2.048 Mb/s 1,024 - Channel Switch 4.096 Mb/s 2,048 - Channel Switch 8.192 Mb/s 4,096 - Channel Switch STo[0:15] ...

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... E1/T1 E1 Trunk Card 15 TC31 E1 247 8 x E1/T1 E1 255 Trunk Card Figure 7 - 256 E1/T1 Digital Access Cross-Connect System (DACS) MT90820 8,192 x 8,192 channel Sixteen MT90820 64 input streams x 64 output streams 24 Zarlink Semiconductor Inc. Data Sheet Switch Matrix operate in 8 Mb/s mode (Figure 9) ...

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... STi1 2Mb/s to 8Mb/s STi7 STo0 MT8986 STo1 8Mb/s to 2Mb/s STo7 Figure 9 - Trunk Card Block Diagram Symbol Zarlink Semiconductor Inc. Data Sheet 32 Streams OUT 32 Streams STo0 256-channel out STo1 (8.192Mb/s pre channel) STi0 256-channel in STi1 (8.192Mb/s pre channel) Min. Max. Units 6 0 ...

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... 2 0 Sym. Level Units Zarlink Semiconductor Inc. Data Sheet Units Test Conditions ° 400 mV noise margin V 400 mV noise margin Units Test Conditions mA Output unloaded µA µA 0≤<V≤V See Note 10mA 10mA OL µA 0 < V < V See Note 1 DD ...

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... HFPS t 20 150 HFPH t 190 300 HCP t 85 150 HCH t 85 150 HCL -10 10 DIF 27 Zarlink Semiconductor Inc. Data Sheet Units Notes ns WFPS Pin = WFPS Pin = 0 ns WFPS Pin = 0 ns WFPS Pin = WFPS Pin = WFPS Pin = WFPS Pin = 1 ns WFPS Pin = 1 ...

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... Typ. Max. Units 0 t SIS t 20 SIH t SOD ODE XCD with timing corrected to cancel time taken to discharge L 28 Zarlink Semiconductor Inc. Data Sheet Test Conditions =200pF =200pF =200pF =30pF =1K, C =200pF, See Note =1K, C =200pF, See Note =1K, C =200pF, See Note 1 L ...

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... Figure 11 - GCI Timing at 2.048 Mb/s and High Speed Serial Interface at 4.096 Mb/s or 8.192 Mb/s, when WFPS pin = 0 MT90820 Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel SIS SIH Bit 7, Channel 0 Bit 6, Channel Bit 1, Channel 0 Bit 2, Channel 0 t SIH Bit 0, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0 29 Zarlink Semiconductor Inc. Data Sheet Bit 5, Channel ...

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... Bit Bit SIS SIH Bit 0, Ch 127 Bit Bit with timing corrected to cancel time taken to discharge L CLK V TT CLK Valid Data HiZ STo t ZD Valid Data HiZ STo t XCD 30 Zarlink Semiconductor Inc. Data Sheet V t HCP t HCH Bit Bit Bit Bit ...

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... DDR t 0 CSRW CSR t 10 DHR ALWR t 0 CSW t 90 DSW t SWD t 10 DHW t AKD t 45 AKH , with timing corrected to cancel time taken to discharge L 31 Zarlink Semiconductor Inc. Data Sheet Max. Units Test Conditions =150pF =150pF, R =1K Note 122 ns ns 55/ ...

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... CSS t 10 DHW t 25 DWS t SWD t 60 RWS t 10 RWH DHR t 10 DSH t AKD t 45 AKH , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet HiZ DATA t CSRW t DHR t DHW t DSW t AKH Max. Units Test Conditions =150pF 122 ns ...

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... ADH t 0 DDR DHR t 20 DSW t SWD t 8 DHW t AKD t 45 AKH , with timing corrected to cancel time taken to discharge L 33 Zarlink Semiconductor Inc. Data Sheet V t RWH DWS DHW DATA t DHR DATA t CSH t t AKH DDR AKD Max. Units Test Conditions ...

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... A0-A7 AD0-AD7 D8-D15 READ AD0-AD7 D8-D15 WRITE DTA Figure 17 - Motorola Non-Multiplexed Bus Timing MT90820 t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t t DSW SWD VALID WRITE DATA t DDR t AKD 34 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH DHR DHW AKH ...

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