AT93C46 ATMEL Corporation, AT93C46 Datasheet

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AT93C46

Manufacturer Part Number
AT93C46
Description
Manufacturer
ATMEL Corporation
Datasheet

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Features
Description
The AT93C46 provides 1024 bits of serial electrically erasable programmable read-
only memory (EEPROM), organized as 64 words of 16 bits each (when the ORG pin is
connected to VCC), and 128 words of 8 bits each (when the ORG pin is tied to
ground). The device is optimized for use in many industrial and commercial applica-
tions where low-power and low-voltage operations are essential. The AT93C46 is
available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead
Ultra Thin mini-MAP (MLP 2x3), 8-lead TSSOP, and 8-lead dBGA2 packages.
The AT93C46 is enabled through the Chip Select pin (CS) and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the
data is clocked out serially on the DO pin. The Write cycle is completely self-timed,
and no separate Erase cycle is required before Write. The Write cycle is only enabled
when the part is in the Erase/Write Enable state. When CS is brought high following
the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part.
The AT93C46 is available in 2.7V to 5.5V and 1.8V to 5.5V versions.
Table 1. Pin Configurations
Pin Name
CS
SK
DI
DO
GND
VCC
ORG
DC
Low-voltage and Standard-voltage Operation
User-selectable Internal Organization
Three-wire Serial Interface
2 MHz Clock Rate (5V)
Self-timed Write Cycle (10 ms max)
High Reliability
Automotive Grade Devices Available
8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead Ultra Thin mini-MAP
(MLP 2x3), 8-lead TSSOP and 8-ball dBGA2 Packages
– 2.7 (V
– 1.8 (V
– 1K: 128 x 8 or 64 x 16
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
CC
CC
= 2.7V to 5.5V)
= 1.8V to 5.5V)
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Internal Organization
Don’t Connect
8-lead Ultra Thin mini-MAP (MLP 2x3)
DO
CS
SK
DI
ORG
GND
DO
VCC
CS
SK
DI
DC
1
2
3
4
Bottom View
8-lead SOIC
8
7
6
5
8-lead PDIP
1
2
3
4
8
7
6
5
8
7
6
5
1
2
3
4
CS
SK
DI
DO
VCC
DC
ORG
GND
VCC
DC
ORG
GND
VCC
DO
CS
SK
DC
CS
SK
DI
ORG
GND
VCC
DC
(1K JEDEC Only)
8-lead TSSOP
1
2
3
4
8-lead dBGA2
1
2
3
4
Bottom View
8-lead SOIC
Rotated (R)
8
7
6
5
1
2
3
4
8
7
6
5
CS
SK
D1
D0
8
7
6
5
ORG
GND
DO
DI
VCC
DC
ORG
GND
Three-wire
Serial
EEPROM
1K (128 x 8 or 64 x 16)
AT93C46
Note:
Not recommended for new
design; please refer to
AT93C46D datasheet.
5140B–SEEPR–2/07
1

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AT93C46 Summary of contents

Page 1

... PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), 8-lead TSSOP, and 8-lead dBGA2 packages. The AT93C46 is enabled through the Chip Select pin (CS) and accessed via a three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK) ...

Page 2

... Meg ohm pullup, then the “x 16” organization is selected. The feature is not available on the 1.8V devices. For the AT93C46, if “x 16” organization is the mode of choice and Pin 6 (ORG) is left unconnected, Atmel recommends using the AT93C46A device. For more details, see the AT93C46A datasheet. Stresses beyond those listed under “ ...

Page 3

Table 2. Pin Capacitance Applicable over recommended operating range from T Symbol Test Conditions C Output Capacitance (DO) OUT C Input Capacitance (CS, SK, DI) IN Note: 1. This parameter is characterized and is not 100% tested. Table 3. ...

Page 4

... SV Valid High t DF Impedance t Write Cycle Time WP (1) Endurance 5.0V, 25°C Note: 1. This parameter is characterized and is not 100% tested. AT93C46 4 = −40° 85° Test Condition 4.5V ≤ V ≤ 5.5V CC 2.7V ≤ V ≤ 5.5V CC 1.8V ≤ V ≤ 5.5V CC 4.5V ≤ V ≤ 5.5V CC 2.7V ≤ ...

Page 5

... The AT93C46 is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host pro- cessor. A valid instruction starts with a rising edge of CS and consists of a start bit (logic “1”) followed by the appropriate op code and the desired memory address location. ...

Page 6

... ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be executed at any time. µs Table 6. Organization Key for Timing Diagrams AT93C46 (1K) I ...

Page 7

Figure 3. READ Timing High Impedance Figure 4. EWEN Timing Figure 5. EWDS Timing 5140B–SEEPR–2/07 ... ... ...

Page 8

... Figure 6. WRITE Timing HIGH IMPEDANCE DO (1) Figure 7. WRAL Timing HIGH IMPEDANCE DO Note: 1. Valid only 4.5V to 5.5V. CC Figure 8. ERASE Timing HIGH IMPEDANCE DO AT93C46 8 ... ... ... N-1 N ... D0 BUSY READY ... D0 N BUSY READY STANDBY CHECK STATUS HIGH IMPEDANCE BUSY READY t WP 5140B–SEEPR–2/07 ...

Page 9

Figure 9. ERAL Timing HIGH IMPEDANCE DO Note: 1. Valid only 4.5V to 5.5V. CC 5140B–SEEPR–2/ STANDBY CHECK STATUS BUSY HIGH IMPEDANCE ...

Page 10

... Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the Table 3 on page 3 and Table 4 on page 4. Not recommended for new design. Please refer to AT93C46D datasheet. 2. “U” designates Green Package and RoHS compliant. 3. “H” designates Green Package and RoHS compliant, with NiPdAu Lead finish 4 ...

Page 11

Packaging Information 8P3 – PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured ...

Page 12

... JEDEC SOIC Top View e Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT93C46 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing ...

Page 13

EIAJ SOIC 1 N Top View e D Side View Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs ...

Page 14

... Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and determined at Datum Plane H. 2325 Orchard Parkway San Jose, CA 95131 R AT93C46 TITLE 8A2, 8-lead, 4 ...

Page 15

PIN 1 BALL PAD CORNER Top View PIN 1 BALL PAD CORNER 1 2 (d1 (e1) Bottom View 8 SOLDER BALLS 1. Dimension “b” is measured at the maximum solder ball diameter. This ...

Page 16

... Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 2325 Orchard Parkway San Jose, CA 95131 R AT93C46 16 A Pin 1 Index ...

Page 17

... Revision History 5140B–SEEPR–2/07 Doc. Rev. Date Comments 5140B 2/2007 Implemented revision history. Added note to page 1 and ordering information; ‘Not recommended for new design; please refer to AT93C46D datasheet’. 17 ...

Page 18

... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life © 2007 Atmel Corporation. All rights reserved. Atmel trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...

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