UDA1350ATS Philips Semiconductors, UDA1350ATS Datasheet

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UDA1350ATS

Manufacturer Part Number
UDA1350ATS
Description
IEC 958 audio DAC
Manufacturer
Philips Semiconductors
Datasheet
Product specification
Supersedes data of 2000 Mar 29
File under Integrated Circuits, IC01
DATA SHEET
UDA1350ATS
IEC 60958 audio DAC
INTEGRATED CIRCUITS
2001 Mar 27

Related parts for UDA1350ATS

UDA1350ATS Summary of contents

Page 1

... DATA SHEET UDA1350ATS IEC 60958 audio DAC Product specification Supersedes data of 2000 Mar 29 File under Integrated Circuits, IC01 INTEGRATED CIRCUITS 2001 Mar 27 ...

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... TIMING CHARACTERISTICS 13 APPLICATION INFORMATION 14 PACKAGE OUTLINE 15 SOLDERING 15.1 Introduction to soldering surface mount packages 15.2 Reflow soldering 15.3 Wave soldering 15.4 Manual soldering 15.5 Suitability of surface mount IC packages for wave and reflow soldering methods 16 DATA SHEET STATUS 17 DEFINITIONS 18 DISCLAIMERS 2 Product specification UDA1350ATS ...

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... UDA1350ATS: – only IEC 60958 input to DAC in SSOP28 package. UDA1350AH: – full featured version in QFP44 package. The UDA1350ATS is a single chip IEC 60958 audio decoder with an integrated stereo digital-to-analog converter employing bitstream conversion techniques. A lock indication signal is available on pin LOCK indicating that the IEC 60958 decoder is locked ...

Page 4

... A-weighted f = 1.0 kHz tone; i code = 0; A-weighted f = 1.0 kHz tone 1.0 kHz tone i PACKAGE DESCRIPTION plastic shrink small outline package; 28 leads 4 Product specification UDA1350ATS MIN. TYP. MAX. UNIT 2.7 3.0 3.6 V 2.7 3.0 3.6 V 8.0 mA 750 A 0 ...

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... V DDD 7 V SSD n.c. 2001 Mar 27 V SSA TEST3 V DDA TEST2 TEST4 UDA1350ATS IEC 60958 DECODER 16 LOCK Fig.1 Block diagram. 5 Product specification UDA1350ATS V DDA(DAC) V ref V SSA(DAC) VOUTR VOUTL DAC DAC NOISE SHAPER INTERPOLATOR 11 AUDIO FEATURE PROCESSOR 5 MGL847 MUTE RESET ...

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... PLL AS analog supply voltage for PLL DIU test pin 4; must be connected to the digital supply voltage (V DIU static pin control selection input not connected DISD test pin 3; must be connected to digital ground (V 6 Product specification UDA1350ATS DESCRIPTION ) SSD ) SSD ) SSD ) DDD ...

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... Mar 27 DESCRIPTION n. TEST3 n. n.c. V DDD 3 26 SELSTATIC TEST1 4 25 TEST4 RESET DDA(PLL) V DDD( SSA(PLL) V SSD DDA UDA1350ATS L3DATA SSA L3CLOCK SSA(DAC) L3MODE ref MUTE 11 18 TEST2 V SSD( VOUTR SPDIF 13 16 LOCK V DDA(DAC VOUTL MGL845 Fig.2 Pin configuration. 7 Product specification UDA1350ATS ...

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... Philips Semiconductors IEC 60958 audio DAC 8 FUNCTIONAL DESCRIPTION The UDA1350ATS is a low cost audio IEC 60958 decoder with an on-board DAC. The minimum audio input sampling frequency conforming to the IEC60958 standard is 28.0 kHz and the maximum audio sampling frequency is 54.0 kHz. 8.1 ...

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... Mbits 48.0 kHz, resulting in a data rate of 3.072 Mbits/s. s The UDA1350ATS supports timing level I, II and III as specified by the IEC 60958 standard. 8.4.2 The audio feature processor automatically provides de-emphasis for the IEC 60958 data stream in the static pin control mode and default mute at start-up in the L3 control mode ...

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... TEST3 0 2001 Mar 27 8.5 Control The UDA1350ATS can be controlled by means of static pins or via the L3 interface. For optimum use of the features of the UDA1350ATS the L3 control mode is recommended since only basic functions are available in the static pin control mode. It should be noted that the static pin control mode and L3 control mode are mutual exclusive ...

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... L3 CONTROL MODE The L3 control mode allows maximum flexibility in controlling the UDA1350ATS. It should be noted that in the L3 control mode several base-line functions are still controlled by pins on the device and that on start-up in the L3 control mode the output is explicitly muted by bit MT via the L3 interface. ...

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... IEC 60958 audio DAC 8.6 L3 interface 8.6.1 G ENERAL The UDA1350ATS has an L3 microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller. The controllable settings are: Restoring L3 defaults Power-on Selection of filter mode and settings of treble and bass ...

Page 13

Acrobat reader. white to force landscape pages to be ... L3 wake-up pulse after power-up L3CLOCK L3MODE device address 0 1 L3DATA DOM bits ...

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... Table 6): 1. One byte starting with ‘01’ for signalling the write action to the device, followed by the device address (‘011000’ for the UDA1350ATS). 2. One byte starting with a ‘0’ for signalling the write action, followed by 7 bits indicating the destination address in binary format with A6 being the MSB and A0 being the LSB ...

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... I NITIALISATION STRING For proper and reliable operation it is needed that the UDA1350ATS is initialized in the L3 control mode. This is needed to have the PLL start up after powering up of the device under all conditions. The initialisation string is given in Table 8. Table 8 L3 init string and set defaults after power-up. ...

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... Acrobat reader. white to force landscape pages to be ... 8.6 VERVIEW OF INTERFACE REGISTERS Table 9 UDA1350ATS register map ADDR FUNCTION D15 D14 D13 D12 Writable settings 00H system PON parameters default ...

Page 17

... Hz. The default value is ‘0000’. Table 13 Bass boost settings BB3 0 FUNCTION FUNCTION 8.6.8.6 = 44.1 kHz the 2-bit value to enable the digital de-emphasis filter. Table 14 De-emphasis selection DE1 LEVEL (dB MIN. MAX Product specification UDA1350ATS Bass boost LEVEL (dB) BB2 BB1 BB0 FLAT ...

Page 18

... MHz Table 18 PLL reset 0 1 RST PLL Product specification UDA1350ATS Auto mute FUNCTION do not mute output during out-of-lock mute output during out-of-lock (default setting) PLL reset FUNCTION normal operation PLL is reset ...

Page 19

... A 2-bit value indicating the timing accuracy of the IEC 60958 input signal is conforming to the IEC 60958 specification. Table 25 Input signal accuracy detection ACC1 FUNCTION FUNCTION 19 UDA1350ATS PCM detection PCM stat FUNCTION 0 input with two channel PCM data 1 input without two channel PCM data ...

Page 20

... ESD pulses of 130 to +130 V. SSA(PLL) CONDITIONS in free air = 48.0 kHz all voltages measured with respect s amb L CONDITIONS power-on power-down DAC in playback mode DAC in Power-down mode 20 Product specification UDA1350ATS MIN. MAX. 2.7 5.0 25 +150 65 +125 40 +85 2000 +2000 200 +200 200 482 ...

Page 21

... V SSA note 1.0 kHz tone dB; A-weighted f = 1.0 kHz tone; code = 0; i A-weighted f = 1.0 kHz tone 1.0 kHz tone i must be connected to the same external power supply unit. 21 Product specification UDA1350ATS MIN. TYP. MAX 0.5 +0. 0.85V DD 0 ...

Page 22

... L3DATA hold time in address and data h(L3)DA transfer mode 2001 Mar + all voltages measured with respect to ground; unless L CONDITIONS f = 32.0 kHz 44.1 kHz 48.0 kHz s 22 Product specification UDA1350ATS MIN. TYP. MAX. UNIT 250 s 97.0 ms 91.0 ms 90.0 ms 500 ns 250 ns 250 ns ...

Page 23

... L3DATA WRITE 2001 Mar 27 t CLK(L3)L t CLK(L3)H t su(L3)A t su(L3)DA t h(L3)DA BIT 0 Fig.8 Timing for address mode. t CLK(L3)L T cy(CLK)L3 t CLK(L3)H t h(L3)DA t su(L3)DA BIT 0 Fig.9 Timing for data transfer mode. 23 Product specification UDA1350ATS t su(L3)A t h(L3)A T cy(CLK)(L3) BIT 7 MGL723 t stp(L3) t h(L3)D BIT 7 MGL882 ...

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... F R38 ( DDD 1 AGND DGND V DDD C42 100 nF ( DDA SSA 21 V DDD(C) 6 L3CLOCK 9 L3MODE 10 11 L3DATA 8 UDA1350ATS 26 SPDIF MGL846 R39 C9 C28 1 k 100 F 100 nF ( lock Fig.10 Test and application diagram. L29 V DDA BZN32A07 C43 C14 100 nF 100 F ( ref ...

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... Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION IEC SOT341-1 2001 Mar 2.5 scale (1) ( 0.38 0.20 10.4 5.4 7.9 0.65 0.25 0.09 10.0 5.2 7.6 REFERENCES JEDEC EIAJ MO-150 25 UDA1350ATS detail 1.03 0.9 1.25 0.2 0.13 0.63 0.7 EUROPEAN PROJECTION Product specification SOT341 (1) y ...

Page 26

... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 26 Product specification UDA1350ATS ...

Page 27

... Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2001 Mar 27 SOLDERING METHOD WAVE not suitable (2) not suitable suitable (3)(4) not recommended (5) not recommended 27 Product specification UDA1350ATS (1) REFLOW suitable suitable suitable suitable suitable ...

Page 28

... Product specification UDA1350ATS DEFINITIONS These products are not Philips Semiconductors ...

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... Philips Semiconductors IEC 60958 audio DAC 2001 Mar 27 NOTES 29 Product specification UDA1350ATS ...

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... Philips Semiconductors IEC 60958 audio DAC 2001 Mar 27 NOTES 30 Product specification UDA1350ATS ...

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... Philips Semiconductors IEC 60958 audio DAC 2001 Mar 27 NOTES 31 Product specification UDA1350ATS ...

Page 32

... Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna Trad Road KM ...

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