UDA1351TS Philips Semiconductors, UDA1351TS Datasheet

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UDA1351TS

Manufacturer Part Number
UDA1351TS
Description
96 kHz IEC 958 audio DAC
Manufacturer
Philips Semiconductors
Datasheet
Product specification
Supersedes data of 2000 Mar 28
File under Integrated Circuits, IC01
DATA SHEET
UDA1351TS
96 kHz IEC 958 audio DAC
INTEGRATED CIRCUITS
2001 Feb 05

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UDA1351TS Summary of contents

Page 1

... DATA SHEET UDA1351TS 96 kHz IEC 958 audio DAC Product specification Supersedes data of 2000 Mar 28 File under Integrated Circuits, IC01 INTEGRATED CIRCUITS 2001 Feb 05 ...

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... TIMING CHARACTERISTICS 13 APPLICATION INFORMATION 14 PACKAGE OUTLINE 15 SOLDERING 15.1 Introduction to soldering surface mount packages 15.2 Reflow soldering 15.3 Wave soldering 15.4 Manual soldering 15.5 Suitability of surface mount IC packages for wave and reflow soldering methods 16 DEFINITIONS 17 LIFE SUPPORT APPLICATIONS 2 Product specification UDA1351TS ...

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... UDA1351TS: – only IEC 958 input to DAC in SSOP28 package. UDA1351H: – full featured version in QFP44 package. The UDA1351TS is a single chip IEC 958 audio decoder with an integrated stereo DAC employing bitstream conversion techniques. A lock indication signal is available on pin LOCK, indicating that the IEC 958 decoder is locked. This pin is also used to indicate whether PCM data is applied to the input or not ...

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... A-weighted = 1.0 kHz tone; code = 0; A-weighted 1.0 kHz tone; code = 0; A-weighted 1.0 kHz tone 1.0 kHz tone i PACKAGE DESCRIPTION 4 Product specification UDA1351TS MIN. TYP. MAX. UNIT 2.7 3.0 3.6 V 2.7 3.0 3.6 V 8.0 mA 750 A 0 ...

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... V SSD 12 V SSD( n.c. 2001 Feb 05 V SSA TEST1 TEST3 V DDA TEST2 TEST4 UDA1351TS IEC 958 DECODER 16 LOCK Fig.1 Block diagram. 5 Product specification UDA1351TS V DDA(DAC) V ref V SSA(DAC) VOUTL VOUTR DAC DAC NOISE SHAPER INTERPOLATOR 11 AUDIO FEATURE PROCESSOR 5 MGU032 MUTE RESET ...

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... PLL AS analog supply voltage for PLL DIU test pin 4; must be connected to the digital supply voltage (V DIU static pin control selection input not connected DISD test pin 3; must be connected to digital ground (V 6 Product specification UDA1351TS DESCRIPTION ) SSD ) SSD ) SSD ) DDD ...

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... Feb 05 DESCRIPTION n. TEST3 n. n.c. V DDD 3 26 SELSTATIC TEST1 4 25 TEST4 RESET DDA(PLL) V DDD( SSA(PLL) V SSD DDA UDA1351TS L3DATA SSA L3CLOCK SSA(DAC) L3MODE ref MUTE 11 18 TEST2 V SSD( VOUTR SPDIF 13 16 LOCK V DDA(DAC VOUTL MGU033 Fig.2 Pin configuration. 7 Product specification UDA1351TS ...

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... Philips Semiconductors 96 kHz IEC 958 audio DAC 8 FUNCTIONAL DESCRIPTION The UDA1351TS is a low cost audio IEC 958 decoder with an on-board DAC. The minimum audio input sampling frequency conforming to the IEC958 standard is 28.0 kHz and the maximum audio sampling frequency is 100.0 kHz. ...

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... Mbits 96.0 kHz, resulting in a data rate of 6.144 Mbits/s. s The UDA1351TS supports timing levels I, II and III, as specified by the IEC 958 standard. 8.4.2 The audio feature processor automatically provides de-emphasis for the IEC 958 data stream in the static pin control mode and default mute at start-up in the L3 control mode ...

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... The output voltage of the FSDAC is scaled proportionally 115 with the power supply voltage. 3.5 8.5 The UDA1351TS can be controlled by means of static pins or via the L3 interface. For optimum use of the features shifts s the UDA1351TS, the L3 control mode is recommended since only basic functions are available in the static pin control mode ...

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... L3 CONTROL MODE The L3 control mode allows maximum flexibility in controlling the UDA1351TS. It should be noted that, in the L3 control mode, several base-line functions are still controlled by pins on the device and that, on start-up in the L3 control mode, the output is explicitly muted by bit MT via the L3 interface. ...

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... Valid PCM data detected Pre-emphasis of the IEC 958 input signal ACcuracy of the Clock (ACC). The exchange of data and control information between the microcontroller and the UDA1351TS is LSB first and is accomplished through a serial hardware L3 interface comprising the following pins: L3DATA: data line L3MODE: mode line L3CLK: clock line ...

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Acrobat reader. white to force landscape pages to be ... L3 wake-up pulse after power-up L3CLOCK L3MODE device address L3DATA 0 1 DOM bits ...

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... Table 6): 1. One byte starting with ‘01’ for signalling the write action to the device, followed by the device address (‘011000’ for the UDA1351TS) 2. One byte starting with a ‘0’ for signalling the write action, followed by seven bits indicating the ...

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... INITIALIZATION STRING For proper and reliable operation, the UDA1351TS must be initialized in the L3 control mode. This is required to have the PLL start up after powering up of the device under all conditions. The initialization string is given in Table 8. Table 8 L3 initialization string and set defaults after power-up. ...

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... Acrobat reader. white to force landscape pages to be ... 8.6 VERVIEW OF INTERFACE REGISTERS Table 9 UDA1351TS register map ADDR FUNCTION D15 D14 D13 D12 Writable settings 00H system PON parameters default ...

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... Hz. The default value is ‘0000’. Table 13 Bass boost settings BB3 0 FUNCTION FUNCTION 8.6.8.6 = 44.1 kHz, the 2-bit value to enable the digital de-emphasis filter. Table 14 De-emphasis selection DE1 LEVEL (dB MIN. MAX Product specification UDA1351TS Bass boost LEVEL (dB) BB2 BB1 BB0 FLAT ...

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... A 1-bit value indicating that the clock regeneration is 0 locked Table 20 PLL lock indication 0 1 PLL lock 18 Product specification UDA1351TS FUNCTION 0 do not mute output during out-of-lock 1 mute output during out-of-lock (default setting) PLL reset FUNCTION 0 normal operation (default) 1 PLL is reset ...

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... IEC 958 input signal conforms to the IEC 958 specification. Table 25 Input signal accuracy detection FUNCTION ACC1 FUNCTION 19 Pre-emphasis detection PRE FUNCTION 0 no pre-emphasis 1 pre-emphasis Clock accuracy detection ACC0 FUNCTION 0 0 level level level III 1 1 undefined Product specification UDA1351TS ...

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... Machine Model (MM); note 125 3.6 V amb note 4 amb DD output short circuited to V output short circuited which can withstand ESD pulses of 130 to +130 V. SSA(PLL) CONDITIONS in free air 20 Product specification UDA1351TS MIN. MAX. UNIT 2.7 5 +150 C 65 +125 C 40 +85 C 2000 +2000 V 200 +200 ...

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... DAC in playback mode DAC in Power-down mode DAC in playback mode DAC in Power-down mode measured with respect to V SSA 21 Product specification UDA1351TS MIN. TYP. MAX. 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3 ...

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... A-weighted f = 1.0 kHz tone; code = 0; i A-weighted f = 1.0 kHz tone; code = 0; i A-weighted f = 1.0 kHz tone 1.0 kHz tone i must be connected to the same external power supply unit. 22 Product specification UDA1351TS MIN. TYP. MAX 100 95 100 96 0.1 0.4 0.2 0.5 3 ...

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... L3DATA hold time in data transfer mode h(L3)R 2001 Feb + all voltages measured with respect to ground; unless L CONDITIONS f = 32.0 kHz 44.1 kHz 48.0 kHz 48.0 kHz s read mode read mode 23 Product specification UDA1351TS MIN. TYP. UNIT 250 s 85.0 ms 63.0 ms 60.0 ms 40.0 ms 500 ns 250 ns 250 ns 190 ns 190 ...

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... CLK(L3)H t su(L3)A t su(L3)DA t h(L3)DA BIT 0 Fig.8 Timing for address mode. t CLK(L3)L T cy(CLK)L3 t CLK(L3)H t h(L3)DA t su(L3)DA BIT 0 t su(L3)R t h(L3)R Fig.9 Timing for data transfer mode. 24 Product specification UDA1351TS t su(L3)A t h(L3)A T cy(CLK)(L3) BIT 7 MGL723 t stp(L3) t h(L3)D t h(L3)DA BIT 7 t dis(L3)DA MGL889 ...

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... F R38 ( DDD 1 AGND DGND V DDD C42 100 nF ( DDA SSA 21 V DDD(C) 6 L3CLOCK 9 L3MODE 10 11 L3DATA 8 UDA1351TS 26 SPDIF MGU035 R39 C9 C28 1 k 100 F 100 nF ( lock Fig.10 Test and application diagram. L29 V DDA BZN32A07 C43 C14 100 nF 100 F ( ref ...

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... Feb 2.5 scale (1) ( 0.38 0.20 10.4 5.4 7.9 0.65 0.25 0.09 10.0 5.2 7.6 REFERENCES JEDEC EIAJ MO-150 detail 1.03 0.9 1.25 0.2 0.13 0.63 0.7 EUROPEAN PROJECTION Product specification UDA1351TS SOT341 ( 1.1 8 0.1 o 0.7 0 ISSUE DATE 95-02-04 99-12-27 ...

Page 27

... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 27 Product specification UDA1351TS ...

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... Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2001 Feb 05 SOLDERING METHOD WAVE not suitable (2) not suitable suitable (3)(4) not recommended (5) not recommended 28 Product specification UDA1351TS (1) REFLOW suitable suitable suitable suitable suitable ...

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... Product specification UDA1351TS (1) These products are not Philips Semiconductors ...

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... Philips Semiconductors 96 kHz IEC 958 audio DAC 2001 Feb 05 NOTES 30 Product specification UDA1351TS ...

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... Philips Semiconductors 96 kHz IEC 958 audio DAC 2001 Feb 05 NOTES 31 Product specification UDA1351TS ...

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... Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna Trad Road KM ...

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