UDA1352TS Philips Semiconductors, UDA1352TS Datasheet
UDA1352TS
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UDA1352TS Summary of contents
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... DATA SHEET UDA1352TS 48 kHz IEC 60958 audio DAC Preliminary specification Supersedes data of 2002 May 22 INTEGRATED CIRCUITS 2002 Nov 22 ...
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... Preliminary specification UDA1352TS SPDIF SIGNAL FORMAT SPDIF channel encoding SPDIF hierarchical layers for audio data SPDIF hierarchical layers for digital data Timing characteristics REGISTER MAPPING SPDIF mute setting (write) Power-down settings (write) Volume control left and right (write) ...
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... By default, the DAC output is muted when the decoder is out-of-lock. However, this setting can be overruled in the 2 L3-bus or I C-bus mode. The UDA1352TS has IEC 60958 input to the DAC only and is in SSOP28 package. Besides the UDA1352TS, the UDA1352HL is also available. The UDA1352HL is the full featured version in LQFP48 package. ...
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... A-weighted f = 1.0 kHz tone; code = 0; A-weighted 1.0 kHz tone i 4 Preliminary specification UDA1352TS MIN. TYP. MAX. UNIT 2.7 3.0 3.6 V 2.7 3.0 3 0.3 ...
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... Nov 22 TEST1 TEST2 2 18 CLOCK AND UDA1352TS C-BUS NON-PCM DATA SYNC DETECTOR IEC 60958 DECODER 1 16 PCMDET LOCK Fig.1 Block diagram. 5 Preliminary specification UDA1352TS V DDA(DAC) V ref V SSA(DAC) VOUTL VOUTR DAC DAC NOISE SHAPER INTERPOLATOR 11 AUDIO FEATURE PROCESSOR 5 MGU655 MUTE RESET ...
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... DAC not connected not connected AGND analog ground for PLL AS analog supply voltage for PLL DISU A1 device address selection input DIU static pin control selection input not connected (reserved) DID A0 device address selection input 6 Preliminary specification UDA1352TS DESCRIPTION ) in application SSD ...
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... V DDD 3 26 SELSTATIC SELIIC 4 25 DA1 RESET DDA(PLL) V DDD( SSA(PLL) V SSD 7 22 n.c. UDA1352TS L3DATA 8 21 n.c. L3CLOCK SSA(DAC) L3MODE ref MUTE 11 18 TEST2 V SSD( VOUTR SPDIF 13 16 LOCK V DDA(DAC VOUTL MGU654 Fig.2 Pin configuration. 7 Preliminary specification UDA1352TS ...
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... PCM data stream is detected or (supposed to be) non-PCM data is detected. 8.2 Mute The UDA1352TS is equipped with a cosine roll-off mute in the DSP data path of the DAC part. Muting the DAC (by pin MUTE or via bit MT in the L3-bus or I will result in a soft mute as shown in Fig.3. The cosine ...
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... Mbits 48.0 kHz, resulting in a data rate of 3.072 Mbits/s. s The UDA1352TS supports timing levels I, II and III, as specified by the IEC 60958 standard. This means that the accuracy of the above mentioned sampling frequencies depends on the timing level III as mentioned in Section 11.4.1. ...
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... Nov 22 8.5 Control The UDA1352TS can be controlled by means of static pins (when pin SELSTATIC = HIGH), via the I pin SELSTATIC = LOW and pin SELIIC = HIGH) or via the L3-bus (when pins SELSTATIC and SELIIC are LOW). For optimum use of the features of the UDA1352TS, the L3-bus or I functions are available in the static pin control mode ...
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... L3 BUS OR BUS MODE 2 The L3-bus or I C-bus mode allows maximum flexibility in controlling the UDA1352TS (see Table 4). It should be noted that in the L3-bus or I and that, on start-up in the L3-bus or I interface. Table 4 Pin description in the L3-bus or I PIN NAME VALUE Mode selection pins ...
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... Valid PCM data detected Pre-emphasis of the IEC 60958 input signal Accuracy of the clock. The exchange of data and control information between the microcontroller and the UDA1352TS is LSB first and is accomplished through the serial hardware L3-bus interface comprising the following pins: L3DATA: data line L3MODE: mode line L3CLOCK: clock line ...
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Acrobat reader. white to force landscape pages to be ... L3 wake-up pulse after power-up L3CLOCK L3MODE device address L3DATA 0 1 DOM bits ...
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... Table 6): 1. One byte starting with ‘01’ for signalling the write action to the device, followed by the device address (‘011000’ for the UDA1352TS default) 2. One byte starting with a ‘0’ for signalling the write action, followed by 7 bits indicating the destination ...
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... Initialization string For proper and reliable operation, the UDA1352TS must be initialized in the L3-bus mode. This is required to have the PLL start-up after powering up of the device under all conditions. The initialization string is given in Table 8. Table 8 L3-bus initialization string and set defaults after power-up ...
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... In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition. 16 Preliminary specification UDA1352TS Start and stop conditions SDA SCL P STOP condition MBC622 2 C-bus ...
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... The device address can be one out of four, being set by pin DA0 and pin DA1. The UDA1352TS acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The UDA1352TS device address is shown in Table 10. ...
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... The first byte (8 bits) contains the device address ‘1001 110’ and a logic 0 (write) for the R/W bit. 3. This is followed by an acknowledge (A) from the UDA1352TS. 4. After this the microcontroller writes the 8-bit register address (ADDR) where the writing of the register content of the UDA1352TS must start. 5. The UDA1352TS acknowledges this register address (A). ...
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... Then the microcontroller generates the device address ‘1001 110’ again, but this time followed by a logic 1 (read) of the R/W bit. An acknowledge is followed from the UDA1352TS. 8. The UDA1352TS sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledge is followed from the microcontroller. ...
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... As shown in Table 14 and Fig.13, the non-PCM encoded data bitstreams are transferred within the basic 16 bits data area of the IEC 60958 sub-frames [time-slots 12 (LSB (MSB)]. 20 Preliminary specification UDA1352TS CHANNEL CODING 0 1 1110 1000 0001 0111 1110 0010 0001 1101 ...
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... S audio sample word B Fig.12 Sub-frame format in audio mode unused S S 16-bit data stream data B B Fig.13 Sub-frame format in non-PCM mode. 21 Preliminary specification UDA1352TS channel 2 M channel 1 W channel 2 frame 191 block validity flag user data channel status parity bit 27 28 ...
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... REFERENCE CONTENTS POINT R R_AC-3 bit bit bit bit bit bit Preliminary specification UDA1352TS VALUE F872 (hex) 4E1F (hex) see Table 16 number of bits REPETITION TIME OF DATA BURST IN IEC 60958 FRAMES none 1536 refer to IEC 60958 384 1152 ...
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... Duty cycle = ------------------- - The duty cycle should be in the range: 40% to 60% when the data bit is a logic 1 45% to 55% when the data bits are two succeeding logic zeros handbook, halfpage 90% 50% 10% 23 Preliminary specification UDA1352TS t H 100 MGU612 Fig.14 Rise and fall times. ...
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... FPLL 68H FPLL status 2002 Nov 22 FUNCTION FUNCTION 24 Preliminary specification UDA1352TS ...
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... If this bit is logic 1, then the output will not be muted in out-of-lock situations. Default value reserved When writing new settings via the L3-bus or I remain at logic 0 (default value) to guarantee correct operation. 2002 Nov Preliminary specification UDA1352TS DESCRIPTION 2 C-bus interface, these bits should always 9 8 MUTEBP 0 1 ...
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... Default value 1. Power control DAC. A 1-bit value to switch the DAC into power-on or Power-down mode. If this bit is logic 0, then the DAC is in Power-down mode. If this bit is logic 1, then the DAC is in power-on mode. Default value 1. 26 Preliminary specification UDA1352TS ...
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... Volume setting right channel. A 8-bit value to program the right channel volume attenuation. The range steps of 0.25 dB steps and dB. Default value 0000 0000; see Table 25. VCL_4 VCL_3 VCL_2 VCR_4 VCR_3 VCR_2 Preliminary specification UDA1352TS VCL_4 VCL_3 VCL_2 VCR_4 VCR_3 VCR_2 DESCRIPTION VCL_1 VCL_0 VOLUME (dB) VCR_1 VCR_0 (default 0. 0 49. ...
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... Default value 0000; see Table 30 reserved Table 28 Sound feature mode flat set (default minimum set maximum set Table 29 Treble settings TR1 2002 Nov TR1 TR0 MODE SELECTION TR0 FLAT SET (dB Preliminary specification 11 10 BB3 BB2 BB1 DESCRIPTION MINIMUM SET (dB) MAXIMUM SET (dB UDA1352TS 9 8 BB0 ...
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... Philips Semiconductors 48 kHz IEC 60958 audio DAC Table 30 Bass boost settings BB3 BB2 BB1 2002 Nov 22 BB0 FLAT SET (dB) MINIMUM SET (dB) MAXIMUM SET (dB Preliminary specification UDA1352TS ...
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... If this bit is logic 1, then the gain is 6 dB. Default value reserved When writing new settings via the L3-bus or I remain at logic 0 (default value) to guarantee correct operation reserved 2002 Nov Preliminary specification DESCRIPTION 2 C-bus interface, these bits should always UDA1352TS ...
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... When writing new settings via the L3-bus or I remain at logic 0 (default value) to guarantee correct operation reserved 2002 Nov Preliminary specification UDA1352TS DESCRIPTION 2 C-bus interface, this bit should always 2 C-bus interface, this bit should always 2 C-bus interface, these bits should always ...
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... Default value When writing new settings via the L3-bus or I remain at logic 0 (default value) to guarantee correct operation. 2002 Nov COMBINE_ PCM 1 DESCRIPTION 2 32 Preliminary specification UDA1352TS BURST_ DET_EN 1 0 C-bus interface, these bits should always ...
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... MUTE_STATE Mute status bit. A 1-bit value to indicate the status of the mute function. If this bit is logic 0, then the audio output is not muted. If this bit is logic 1, then the mute sequence has been completed and the audio output is muted reserved 2002 Nov Preliminary specification UDA1352TS MUTE_ STATE DESCRIPTION 8 0 ...
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... SPDIFIN_LOCK SPDIF lock indicator. A 1-bit value to signal whether the SPDIF decoder block is in lock or not. If this bit is logic 0, then the decoder block is out-of-lock. If this bit is logic 1, then the decoder block is in lock. 2002 Nov Preliminary specification UDA1352TS BURST_ B_ERR DET DESCRIPTION ...
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... SPDI_ SPDI_ BIT21 BIT20 [39:32 SPDI_ SPDI_ BIT37 BIT36 [15: SPDI_ SPDI_ BIT13 BIT12 5 4 SPDI_ SPDI_ BIT5 BIT4 35 Preliminary specification UDA1352TS SPDI_ SPDI_ SPDI_ BIT11 BIT10 BIT9 SPDI_ SPDI_ SPDI_ BIT3 BIT2 BIT1 SPDI_ SPDI_ SPDI_ BIT27 BIT26 BIT25 3 2 ...
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... SPDI_ SPDI_ SPDI_ BIT29 BIT28 BIT27 5 4 SPDI_ SPDI_ SPDI_ BIT21 BIT20 BIT19 [39:32 SPDI_ SPDI_ SPDI_ BIT37 BIT36 BIT35 DESCRIPTION 36 Preliminary specification UDA1352TS SPDI_ SPDI_ BIT26 BIT25 SPDI_ SPDI_ BIT18 BIT17 SPDI_ SPDI_ BIT34 BIT33 8 SPDI_ BIT24 0 SPDI_ ...
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... A (left for stereo transmission (right for stereo transmission Preliminary specification UDA1352TS WORD LENGTH SPDI_BIT32 = 1 word length not indicated (default) 20 bits 22 bits reserved 23 bits 24 bits 21 bits reserved SAMPLING FREQUENCY CHANNEL NUMBER ...
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... Philips Semiconductors 48 kHz IEC 60958 audio DAC SPDI_BIT23 SPDI_BIT22 SPDI_BIT21 SPDI_BIT20 Table 52 Source number SPDI_BIT19 SPDI_BIT18 SPDI_BIT17 SPDI_BIT16 2002 Nov don’t care Preliminary specification UDA1352TS CHANNEL NUMBER SOURCE NUMBER ...
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... Preliminary specification UDA1352TS FUNCTION MODE AUDIO SAMPLE SPDI_BIT1 = 1 default state for applications other than linear PCM other states reserved ...
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... VCO_TIMEOUT VCO time-out. A 1-bit value that indicates the FPLL status together with bit 8; see Table 58 reserved Table 58 Lock status indicators of the FPLL FPLL_LOCK 2002 Nov VCO_ TIMEOUT DESCRIPTION VCO_TIMEOUT Preliminary specification UDA1352TS FPLL_ LOCK FUNCTION FPLL out-of-lock FPLL time-out FPLL in lock FPLL time-out ...
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... all voltages measured with respect s amb L CONDITIONS 2.7 2.7 2.7 2.7 2.7 power-on power-down; clock off DAC in playback mode DAC in Power-down mode 41 Preliminary specification UDA1352TS MIN. MAX. UNIT 2.7 5 +125 C 40 +85 C 2000 +2000 V 200 +200 V ...
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... V SSA f = 1.0 kHz tone dBFS at 40 dBFS; A-weighted f = 1.0 kHz tone; code = 0; i A-weighted f = 1.0 kHz tone i must be connected to the same external power supply unit. 42 Preliminary specification UDA1352TS MIN. TYP. MAX. 0. 0.5 V DDD DDD 0.5 +0.2V DDD ...
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... BUF condition 2002 Nov + all voltages measured with respect to ground; unless L CONDITIONS f = 32.0 kHz 44.1 kHz 48.0 kHz s note 1 note 1 43 Preliminary specification UDA1352TS MIN. TYP. MAX. 250 85.0 63.0 60.0 500 250 250 190 190 190 190 190 190 ...
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... L3MODE t h(L3)A L3CLOCK L3DATA 2002 Nov 22 CONDITIONS t CLK(L3)L t CLK(L3)H t su(L3)A t su(L3)DA t h(L3)DA BIT 0 Fig.15 Timing for address mode. 44 Preliminary specification UDA1352TS MIN. TYP. MAX. 100 400 t su(L3)A t h(L3)A T cy(CLK)(L3) BIT 7 MGL723 UNIT ...
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... HD;DAT S 2002 Nov 22 t CLK(L3)L T cy(CLK)L3 t CLK(L3)H t h(L3)DA t su(L3)DA BIT 0 t d(L3)R Fig.16 Timing for data transfer mode SU;DAT t SU;STA t HIGH Sr 2 Fig.17 Timing of the I C-bus transfer. 45 Preliminary specification UDA1352TS t h(L3)D BIT 7 t dis(L3)R MBL566 t HD;STA BUF t SU;STO P S MSC610 ...
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... V) ( DDA DDD C20 C21 100 F 100 F (16 V) (16 V) GND DDD RST 2 NORM 3 n.c. n.c. n.c. V SSA(PLL) V DDA(PLL) TEST2 RESET UDA1352TS PCMDET LOCK DA0 DA1 HLMP-1385 (2x) Fig.18 Application diagram. Vref C15 C14 100 (50 V) (16 V) C17 X2 R5 VOUTL left_out 100 (16 V) ...
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... Nov 2.5 scale (1) ( 0.38 0.20 10.4 5.4 7.9 0.65 0.25 0.09 10.0 5.2 7.6 REFERENCES JEDEC EIAJ MO-150 47 Preliminary specification detail 1.03 0.9 1.25 0.2 0.13 0.63 0.7 EUROPEAN PROJECTION UDA1352TS SOT341 ( 1.1 8 0.1 o 0.7 0 ISSUE DATE 95-02-04 99-12-27 ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 48 Preliminary specification UDA1352TS ...
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... Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 Nov 22 (1) not suitable not suitable suitable not recommended not recommended 49 Preliminary specification UDA1352TS SOLDERING METHOD (2) WAVE REFLOW suitable (3) suitable suitable (4)(5) suitable ...
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... Preliminary specification UDA1352TS DEFINITION These products are not Philips Semiconductors ...
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... Philips. This specification can be ordered using the code 9398 393 40011. 2002 Nov 22 C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 51 Preliminary specification UDA1352TS 2 C patent to use the 2 C specification defined by ...
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... Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. ...