MC68HC705C9ACS Motorola, MC68HC705C9ACS Datasheet
MC68HC705C9ACS
Specifications of MC68HC705C9ACS
Related parts for MC68HC705C9ACS
MC68HC705C9ACS Summary of contents
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... M68HC05 Microcontrollers WWW.MOTOROLA.COM/SEMICONDUCTORS MC68HC705C9A Advance Information MC68HC705C9A/D Rev. 4, 2/2002 ...
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...
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... The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Motorola and are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. MC68HC705C9A — Rev. 4.0 MOTOROLA © Motorola, Inc., 2002 Advance Information ...
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... Format update to current publication standards Figure 12-10. SPI Slave Timing Diagram labels for MISO and MOSI and subtitle for part b. Figure 8-3. Timer Status Register (TSR) address designator from $0012 to $0013. Page Number(s) N/A — Corrected 145 — Corrected 78 MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... Section 10. Serial Peripheral Interface (SPI 103 Section 11. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 115 Section 12. Electrical Specifications 131 Section 13. Mechanical Specifications . . . . . . . . . . . . . 147 Section 14. Ordering Information . . . . . . . . . . . . . . . . . 151 Appendix A. EPROM Programming 153 Appendix B. M68HC05Cx Family MC68HC705C9A — Rev. 4.0 MOTOROLA Interface (SCI Feature Comparisons . . . . . . . . . . . . . . . . 157 List of Sections List of Sections Advance Information 5 ...
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... List of Sections Advance Information 6 List of Sections MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... MC68HC705C9A — Rev. 4.0 MOTOROLA Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Port B Mask Option Register (PBMOR C12 Mask Option Register (C12MOR Software-Programmable Options (MC68HC05C9A Mode Only Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ...
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... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Accumulator ( Index Register ( Program Counter (PC .49 Stack Pointer (SP Condition Code Register (CCR Section 4. Interrupts Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Non-Maskable Software Interrupt (SWI External Interrupt (IRQ or Port Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SPI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table of Contents MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... MC68HC705C9A — Rev. 4.0 MOTOROLA Section 5. Resets Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Power-On Reset (POR RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .60 MC68HC05C9A Compatible COP . . . . . . . . . . . . . . . . . . . . . . 60 C9A COP Reset Register C9A COP Control Register MC68HC05C12A Compatible COP . . . . . . . . . . . . . . . . . . . . . 63 MC68HC05C12A Compatible COP Clear Register ...
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... Alternate Timer Registers Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Output Compare Registers Timer During Wait Mode Timer During Stop Mode Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SCI Receiver Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SCI Transmitter Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Receiver Wakeup Operation Idle Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table of Contents MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... MC68HC705C9A — Rev. 4.0 MOTOROLA Address Mark Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Receive Data In (RDI Start Bit Detection Transmit Data Out (TDO .94 SCI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SCI Control Register .95 SCI Control Register .96 SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Baud Rate Register ...
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... Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Section 12. Electrical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Power Considerations 133 5.0-Vdc Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 135 3.3-Vdc Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 136 5.0-Vdc Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.3-Vdc Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table of Contents MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... A.1 A.2 A.3 A.4 A.5 MC68HC705C9A — Rev. 4.0 MOTOROLA Section 13. Mechanical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03 148 42-Pin Plastic Shrink Dual In-Line (SDIP) Package (Case 858-01 148 44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02) ...
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... Table of Contents Advance Information 14 Table of Contents MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... MC68HC705C9A — Rev. 4.0 MOTOROLA Title Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Port B Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Mask Option Register C9A Option Register 40-Pin PDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 30 42-Pin SDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 31 44-Lead PLCC Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . 32 44-Pin QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 33 C9A Memory Map ...
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... SCI Examples of Start Bit Sampling Techniques . . . . . . . . . . . 92 SCI Sampling Technique Used on All Bits . . . . . . . . . . . . . . . . 92 SCI Artificial Start Following a Frame Error . . . . . . . . . . . . . . . 93 SCI Start Bit Following a Break . . . . . . . . . . . . . . . . . . . . . . . .94 SCI Data Register (SCDR SCI Control Register 1 (SCCR1 Clock Frequency 5 137 DD Clock Frequency 3 137 DD List of Figures Page MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... Plastic DIP Package (Case 711-03 148 13-2 42-Pin Plastic SDIP Package (Case 858-01 148 13-3 44-Lead PLCC (Case 777-02 149 13-4 44-Lead QFP (Case 824A-01 150 A-1 MC68HC705C9A — Rev. 4.0 MOTOROLA Title EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . .154 List of Figures List of Figures Page ...
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... List of Figures Advance Information 18 MC68HC705C9A — Rev. 4.0 List of Figures MOTOROLA ...
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... Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 11-7 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 14-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 A-1 A-2 B-1 MC68HC705C9A — Rev. 4.0 MOTOROLA Title Vector Addresses for Interrupts and Resets .52 COP Timeout Period Baud Rate Generator Clock Prescaling . . . . . . . . . . . . . . . . . 101 Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Bootloader Functions ...
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... List of Tables Advance Information 20 MC68HC705C9A — Rev. 4.0 List of Tables MOTOROLA ...
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... Introduction The MC68HC705C9A HCMOS microcomputer is a member of the M68HC05 Family. The MC68HC705C9A is the EPROM version of the MC68HC05C9A and also can be configured as the EPROM version of MC68HC705C9A — Rev. 4.0 MOTOROLA Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Port B Mask Option Register (PBMOR C12 Mask Option Register (C12MOR) ...
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... No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the EPROM difficult for unauthorized users. Advance Information 22 Programmable mask option register (MOR) for C9A/C12A configuration Programmable MOR for port B pullups and interrupts ...
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... COP WATCHDOG DIVIDE BY FOUR TIMER CLOCK CAPTURE/ TCAP COMPARE TCMP TIMER V DD POWER V SS MC68HC705C9A — Rev. 4.0 MOTOROLA ARITHMETIC/LOGIC UNIT ACCUMULATOR INDEX REGISTER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER CPU CLOCK DIVIDE BY TWO INTERNAL CLOCK BAUD RATE GENERATOR SPI ...
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... C9A COP and clock monitor. The C12 COP clear register ($3FF0) is disabled. The port D data direction register ($0007) is enabled, allowing output capability on the seven port D pins. General Description MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... MC68HC705C9A — Rev. 4.0 MOTOROLA SPI output signals (MOSI, MISO, and SCK) require the corresponding bits in the port D data direction register to be set for output. The port D wire-OR mode control bit (bit 5 of SPCR $000A) is enabled, allowing open-drain configuration of port D. ...
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... External Interrupt (IRQ or Port Bit PBPU7 PBPU6 PBPU5 PBPU4 Figure 1-2. Port B Mask Option Register 1 = Pullup and CPU interrupt enabled 0 = Pullup and CPU interrupt disabled General Description 1-2, contains eight B)). Bit 0 PBPU3 PBPU2 PBPU1 PBPU0 MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... NOTE: Any Port B pin configured for interrupt capability will follow the same edge or edge/level trigger as the IRQ pin. MC68HC705C9A — Rev. 4.0 MOTOROLA Select between MC68HC05C9A/C12A configuration Enable/disable stop mode (C12A mode only) Enable/disable COP (C12A mode only) Edge-triggered only or edge- and level-triggered external interrupt pin (IRQ pin) (C12A mode only) ...
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... If the MCU enters stop mode, the clock monitor is enabled to force a system reset 0 = STOP instruction executed as normal 1 = When in C12A mode, this enables the C12ACOP watchdog timer When in C12A mode, this disables the C12ACOP watchdog timer Security enabled 0 = Security disabled General Description Mode.) If MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... This bit is set by reset, but can be cleared by software. This bit can be written only once. MC68HC705C9A — Rev. 4.0 MOTOROLA Software-Programmable Options (MC68HC05C9A Mode Only) Map two different areas of memory between RAM and EPROM, one of 48 bytes and one of 128 bytes ...
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... PB4 16 PB5 17 PB6 18 PB7 Figure 1-5. 40-Pin PDIP Pin Assignments General Description Figure 1-8 show the pin OSC1 38 OSC2 37 TCAP 36 PD7 35 TCMP 34 PD5/SS 33 PD4/SCK 32 PD3/MOSI 31 PD2/MISO 30 PD1/TDO 29 PD0/RDI 28 PC0 27 PC1 26 PC2 25 PC3 24 PC4 23 PC5 22 PC6 21 PC7 MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... MC68HC705C9A — Rev. 4.0 MOTOROLA RESET 1 IRQ PA7 4 PA6 5 PA5 6 PA4 7 PA3 8 PA2 9 PA1 10 PA0 11 PB0 12 PB1 13 PB2 14 PB3 15 N/C 16 PB4 17 PB5 18 PB6 19 PB7 Figure 1-6. 42-Pin SDIP Pin Assignments General Description General Description Functional Pin Descriptions OSC1 40 OSC2 39 TCAP 38 PD7 ...
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... Advance Information 32 1 PA5 7 8 PA4 9 PA3 10 PA2 11 PA1 12 PA0 PB0 13 14 PB1 15 PB2 16 PB3 N/C 17 Figure 1-7. 44-Lead PLCC Pin Assignments General Description N/C 39 TCMP 38 PD5/SS 37 PD4/SCK 36 PD3/MOSI 35 PD2MISO 34 PD1/TDO 33 PD0/RDI 32 PC0 31 PC1 30 PC2 29 MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... V and Power is supplied to the MCU using these two pins. V supply and V 1.7 This pin provides the programming voltage to the EPROM array. For normal operation, V MC68HC705C9A — Rev. 4.0 MOTOROLA 1 PA6 2 PA5 3 PA4 4 PA3 5 PA2 6 PA1 7 PA0 8 PB0 9 PB1 10 PB2 11 PB3 Figure 1-8 ...
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... The TCMP pin provides an output for the output compare feature of the on-chip programmable timer. Refer to Timer Advance Information 34 for more detail. for more detail. for more detail. for more detail. General Description Section 8. Capture/Compare Section 8. Capture/Compare MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... D pins are configured as inputs during reset. When configured as a C12A, the port D pins are input only. Refer to more detail. MC68HC705C9A — Rev. 4.0 MOTOROLA Section 7. Input/Output Ports for more detail. Section 7. Input/Output Ports General Description ...
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... General Description Advance Information 36 General Description MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... When configured as an MC68HC05C12A, the section of the memory map from $0020 to $004F is fixed as EPROM and the section from $0100 to $0FFF becomes unused. MC68HC705C9A — Rev. 4.0 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 EPROM .38 EPROM Security ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 I/O Registers ...
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... Locations $3FF0 and $3FF1 are the mask option registers (MOR) (see 1.5 Mask For detailed information on programming the EPROM see EPROM Advance Information 38 and Figure 2-2.) These may be accessed at any time by 1.6 Software-Programmable Options for additional information. Options). Programming. Memory Appendix A. MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... MASK OPTION REGISTERS $3FF1 $3FF2 USER EPROM VECTORS 14 BYTES $3FFF MC68HC705C9A — Rev. 4.0 MOTOROLA PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER PORT D DATA REGISTER PORT A DATA DIRECTION REGISTER PORT B DATA DIRECTION REGISTER PORT C DATA DIRECTION REGISTER PORT D DATA DIRECTION REGISTER ...
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... UNUSED $001D UNUSED $001E UNUSED $001F UNUSED $3FF0 $3FF1 $3FF2 UNUSED UNUSED $3FF3 $3FF4 $3FF5 $3FF6 $3FF7 $3FF8 $3FF9 $3FFA $3FFB $3FFC $3FFD $3FFE $3FFF MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... I/O, control and status registers are located within one 32-byte block in page zero of the address space ($0000–$001F). A summary of these registers is shown in contents of these registers is given MC68HC705C9A — Rev. 4.0 MOTOROLA Appendix A. EPROM Programming. Figure 2-3. More detail about the Figure 2-4 ...
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... Timer Register Low $001A Alternate Timer Register High $001B Alternate Timer Register Low $001C EPROM Programming Register $001D C9A COP Reset Register $001E C9A COP Control Register $001F Reserved Figure 2-3. I/O Register Summary Memory MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... See page 70. Port C Data Direction Register $0006 (DDRC) See page 71. Port D Data Direction Register $0007 (DDRD) C9A Only See page 71. $0008 Unimplemented Figure 2-4. Input/Output Registers (Sheet MC68HC705C9A — Rev. 4.0 MOTOROLA Bit Read: PA7 PA6 PA5 Write: Reset: Read: PB7 PB6 ...
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... SCD7 SDC6 SCD5 SCD4 Write: Unaffected by reset = Unimplemented Memory CPOL CPHA SPR1 SPD3 SPD2 SPD1 SCR2 SCR1 0 — WAKE ILIE TE RE RWU SCD3 SCD2 SCD1 R = Reserved U = Unaffected MC68HC705C9A — Rev. 4.0 MOTOROLA Bit 0 SPR0 U 0 SPD0 SCR0 U 0 SBK 0 — SCD0 ...
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... Timer Register High $0018 (TRH) See page 79. Timer Register Low (TRL) $0019 See page 79. Alternate Timer Register High $001A (ATRH) See page 80. Figure 2-4. Input/Output Registers (Sheet MC68HC705C9A — Rev. 4.0 MOTOROLA Bit Read: ICIE OCIE TOIE Write: Reset Read: ICF ...
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... Bit 6 Bit 5 Bit 4 Write Read: Write Read: Write: Bit 7 Bit 6 Bit 5 Bit Read COPF Write Unimplemented Memory Bit 3 Bit 2 Bit LATCH Bit 3 Bit 2 Bit CME COPE CM1 Reserved U = Unaffected MC68HC705C9A — Rev. 4.0 MOTOROLA Bit 0 Bit 0 0 EPGM 0 Bit 0 0 CM0 0 R ...
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... This section contains the basic programmers model and the registers contained in the CPU. 3.3 CPU Registers The MCU contains five registers as shown in the programming model of Figure MC68HC705C9A — Rev. 4.0 MOTOROLA Section 3. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Accumulator ( Index Register ( Program Counter (PC) ...
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... CONDITION CODE REGISTER R ACCUMULATOR E INCREASING T MEMORY INDEX REGISTER U ADDRESSES R N PCH PCL UNSTACK Figure 3-2. Interrupt Stacking Order Central Processor Unit (CPU) 0 ACCUMULATOR 0 INDEX REGISTER 0 PROGRAM COUNTER 0 SP STACK POINTER CCR CONDITION CODE REGISTER 0 STACK DECREASING R MEMORY R ADDRESSES MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... When this bit is set, the timer, SCI, SPI, and external interrupt are masked (disabled interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt bit is cleared. MC68HC705C9A — Rev. 4.0 MOTOROLA Central Processor Unit (CPU) Central Processor Unit (CPU) CPU Registers Advance Information ...
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... When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates. Advance Information 50 Central Processor Unit (CPU) MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. MC68HC705C9A — Rev. 4.0 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Non-Maskable Software Interrupt (SWI External Interrupt (IRQ or Port Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SCI Interrupt ...
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... TOIE bit TCIE bit I bit RIE bit ILIE bit SPIE I bit Interrupts Priority Vector (1 = Highest) Address 1 $3FFE–$3FFF Same priority $3FFC–$3FFD as instruction 2 $3FFA–$3FFB 3 $3FF8–$3FF9 4 $3FF6–$3FF7 5 $3FF4–$3FF5 MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... C12IRQ bit in the C12 mask option register ($3FF1). NOTE: The internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse can be latched and serviced as soon as the I bit is cleared. MC68HC705C9A — Rev. 4.0 MOTOROLA Non-Maskable Software Interrupt (SWI) Interrupts Interrupts 7.4 Port B. ...
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... The interrupt flags are in the SPI status register (SPSR), and the enable bits are in the SPI control register (SPCR). Either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $3FF4 and $3FF5. Advance Information 54 MC68HC705C9A — Rev. 4.0 Interrupts MOTOROLA ...
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... Y RESTORE REGISTERS FROM STACK: CCR,A,X,PC MC68HC705C9A — Rev. 4.0 MOTOROLA FROM RESET I BIT IN CCR SET? N IRQ OR PORT B Y EXTERNAL INTERRUPT N INTERNAL Y TIMER INTERRUPT N INTERNAL Y SCI INTERRUPT N INTERNAL Y SPI INTERRUPT N FETCH NEXT INSTRUCTION SWI Y INSTRUCTION ? N RTI Y INSTRUCTION ? N EXECUTE INSTRUCTION Figure 4-1. Interrupt Flowchart ...
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... Interrupts Advance Information 56 MC68HC705C9A — Rev. 4.0 Interrupts MOTOROLA ...
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... MC68HC705C9A — Rev. 4.0 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Power-On Reset (POR RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .60 MC68HC05C9A Compatible COP . . . . . . . . . . . . . . . . . . . . . . 60 C9A COP Reset Register C9A COP Control Register MC68HC05C12A Compatible COP . . . . . . . . . . . . . . . . . . . . . 63 MC68HC05C12A Compatible COP Clear Register . . . . . . . . . 64 COP During Wait Mode ...
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... RESET is driven high externally. Advance Information 58 CLOCK MONITOR COP WATCHDOG V POWER-ON RESET DD STOP INTERNAL CLOCK Figure 5-1. Reset Sources ) oscillator stabilization delay after the cyc Resets Figure 5 block diagram R RST TO CPU AND D Q SUBSYSTEMS RESET LATCH . DD MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence. 4. RESET outputs V during 4064 power-on reset cycles when in C9A mode only. OL Figure 5-2. Power-On Reset and RESET MC68HC705C9A — Rev. 4.0 MOTOROLA NEW NEW 3FFE 3FFE PC ...
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... COP and clock monitor functions. Figure 5-3 INTERNAL CPU CLOCK 16 BIT TIMER SYSTEM COPRST Figure 5-3. C9A COP Block Diagram Advance Information 60 shows a block diagram of the MC68HC05C9A COP Resets CM1 CM0 COP MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... COP timeout period. If the COP should time out, a system reset will occur and the device will be re-initialized in the same fashion as a power-on reset or reset. Reading this register does not return valid data. MC68HC705C9A — Rev. 4.0 MOTOROLA Bit Bit 7 Bit 6 ...
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... Figure 5-5. COP Control Register (COPCR COP or clock monitor reset has occurred COP or clock monitor reset has occurred Clock monitor enabled 0 = Clock monitor disabled 1 = COP enabled 0 = COP disabled Resets Figure 5-5, performs these CME COPE CM1 MC68HC705C9A — Rev. 4.0 MOTOROLA Bit 0 CM0 0 ...
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... This COP is implemented with an 18-bit ripple counter. This provides a timeout period of 64 milliseconds at a bus rate (f should time out, a system reset will occur and the device will be re- initialized in the same fashion as a power-on reset or reset. MC68HC705C9A — Rev. 4.0 MOTOROLA Table 5-1. COP Timeout Period 15 CM0 f ...
Page 64
... COP counter will not be reset after the 4064-cycle delay and will have that many cycles already counted when control is returned to the program. Advance Information 64 Figure Bit Unimplemented U = Undetermined Figure 5-6. COP Clear Register (COPCLR) Resets 5-6, resets the C12A COP Bit 0 COPC MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 65
... If the CPU executes a STOP instruction, the clock monitor will provide a system reset. NOTE: This feature cannot be used with operating frequencies of 200 kHz or less. MC68HC705C9A — Rev. 4.0 MOTOROLA Reset) and one available in C12A mode (see Option). Resets Resets COP During Stop Mode 5 ...
Page 66
... Resets Advance Information 66 MC68HC705C9A — Rev. 4.0 Resets MOTOROLA ...
Page 67
... All other registers and memory remain unaltered. All input/output lines remain unchanged. The processor can be brought out of the stop mode only by an external interrupt or reset. See MC68HC705C9A — Rev. 4.0 MOTOROLA Section 6. Low-Power Modes Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Wait Mode ...
Page 68
... The timer, SCI, and SPI may be enabled to allow a periodic exit from the wait mode. Advance Information LIH t 4064 t ILCH cyc 3FFE Low-Power Modes 3FFE 3FFE 3FFE 3FFF RESET OR INTERRUPT VECTOR FETCH MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 69
... Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing DDR bit sets the corresponding port bit to output mode. A block diagram of the port logic is shown in MC68HC705C9A — Rev. 4.0 MOTOROLA Section 7. Input/Output (I/O) Ports Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Port Port Port C ...
Page 70
... The port B logic is shown in Figure Advance Information 70 DATA DIRECTION REGISTER BIT LATCHED OUTPUT DATA BIT Figure 7-1. Port A I/O Circuit 7-2. Input/Output (I/O) Ports I/O OUTPUT PIN INPUT REG BIT INPUT I/O MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 71
... SCI and SPI subsystems are disabled, thereby returning the ports to inputs. Writing DDR bit sets the corresponding port bit to output mode only when configured as a C9A. MC68HC705C9A — Rev. 4.0 MOTOROLA Input/Output (I/O) Ports Input/Output (I/O) Ports Port C Figure 7-1 ...
Page 72
... EXTERNAL INTERRUPT VECTOR FETCH Advance Information DISABLED ENABLED DATA DIRECTION REGISTER B BIT DDRB7 PORT B DATA REGISTER BIT PB7 EDGE ONLY EDGE AND LEVEL Figure 7-2. Port B I/O Logic Input/Output (I/O) Ports V DD PBX EXTERNAL INTERRUPT REQUEST I BIT (FROM CCR) MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 73
... Introduction This section describes the operation of the 16-bit capture/compare timer. Figure 8-1 MC68HC705C9A — Rev. 4.0 MOTOROLA Section 8. Capture/Compare Timer Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Timer I/O Registers .76 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Timer Status Register Timer Registers ...
Page 74
... Figure 8-1. Capture/Compare Timer Block Diagram Capture/Compare Timer HIGH LOW BYTE BYTE LOW BYTE INPUT $14 $18 CAPTURE $15 $19 REGISTER $1A $1B EDGE DETECT CIRCUIT D Q CLK OUTPUT LEVEL C REG. TIMER CONTROL RESET IEDG OLVL REG. $12 OUTPUT LEVEL (TCMP) MC68HC705C9A — Rev. 4.0 MOTOROLA EDGE INPUT (TCAP) ...
Page 75
... The programmer can use the output compare register to measure time periods, to generate timing delays generate a pulse of specific duration or a pulse train of specific frequency and duty cycle on the TCMP pin. MC68HC705C9A — Rev. 4.0 MOTOROLA Capture/Compare Timer Capture/Compare Timer Timer Operation Advance Information ...
Page 76
... Controls the active edge polarity of the TCAP signal Controls the active level of the TCMP output Bit ICIE OCIE TOIE Unimplemented U = Undetermined Figure 8-2. Timer Control Register (TCR) Capture/Compare Timer Figure 8-2, performs these Bit IEDG OLVL MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 77
... The state of this read/write bit determines whether a logic 1 or logic 0 appears on the TCMP pin when a successful output compare occurs. Resets clear the OLVL bit. MC68HC705C9A — Rev. 4.0 MOTOROLA 1 = Input capture interrupts enabled 0 = Input capture interrupts disabled 1 = Output compare interrupts enabled ...
Page 78
... A match between the 16-bit counter and the output compare registers, transferring the OLVL bit to the TCMP pin A timer roll over from $FFFF to $0000 Bit ICF OCF TOF Unimplemented U = Undetermined Figure 8-3. Timer Status Register (TSR) Capture/Compare Timer Figure 8-3, contains flags Bit MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 79
... TRL causes TRL to be latched until TRL is read. Reading TRL after reading the timer status register clears the timer overflow flag (TOF). Writing to the timer registers has no effect. TRH $0018 Read: Write Reset: TRL $0019 Read: Write: Reset: MC68HC705C9A — Rev. 4.0 MOTOROLA Bit Bit 15 Bit 14 Bit 13 Bit Bit 7 ...
Page 80
... ATRH, and clear the flag after reading ATRL. Advance Information 80 Bit Bit 15 Bit 14 Bit 13 Bit Bit Bit 7 Bit 6 Bit 5 Bit Unimplemented Figure 8-5. Alternate Timer Registers (ATRH and ATRL) Capture/Compare Timer Figure 8- Bit 0 Bit 11 Bit 10 Bit 9 Bit Bit 0 Bit 3 Bit 2 Bit 1 Bit MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 81
... Read: Write: Reset: NOTE: To prevent interrupts from occurring between readings of ICRH and ICRL, set the interrupt flag in the condition code register before reading ICRH, and clear the flag after reading ICRL. MC68HC705C9A — Rev. 4.0 MOTOROLA Bit Bit 15 Bit 14 Bit 13 Bit 12 ...
Page 82
... Enable interrupts by clearing the I bit in the condition code register. Advance Information 82 Bit Bit 15 Bit 14 Bit 13 Bit 12 Unaffected by reset Bit Bit 7 Bit 6 Bit 5 Bit 4 Unaffected by reset Capture/Compare Timer Bit 0 Bit 11 Bit 10 Bit 9 Bit Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 83
... If reset is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred. MC68HC705C9A — Rev. 4.0 MOTOROLA Capture/Compare Timer Capture/Compare Timer Timer During Wait Mode ...
Page 84
... Capture/Compare Timer Advance Information 84 Capture/Compare Timer MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 85
... MC68HC705C9A — Rev. 4.0 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SCI Receiver Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SCI Transmitter Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Receiver Wakeup Operation Idle Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Address Mark Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Receive Data In (RDI Start Bit Detection Transmit Data Out (TDO) ...
Page 86
... Interrupt-driven operation capability with five interrupt flags: – Transmitter data register empty – Transmission complete – Transmission data register full – Receiver overrun – Idle receiver input Receiver framing error detection 1/16 bit-time noise detection Serial Communications Interface (SCI) MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 87
... Figure 9-1. Serial Communications Interface Block Diagram NOTE: The serial communications data register (SCI SCDR) is controlled by the internal R/W signal the transmit data register when written to and the receive data register when read. MC68HC705C9A — Rev. 4.0 MOTOROLA SCI INTERRUPT + & & & ...
Page 88
... Receiver wakeup function (idle line or address bit) Idle line detection Framing error detection Noise detection Overrun detection Receiver data register full flag Transmit data register empty flag Transmit complete flag Send break Serial Communications Interface (SCI) Figure 9-1. Option bits in serial MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 89
... A valid character must be received before the idle line condition or the IDLE bit will not be set and idle line interrupt will not be generated. OSC FREQ ³ OSC MC68HC705C9A — Rev. 4.0 MOTOROLA SCP0–SCP1 SCI PRESCALER BUS FREQ SELECT ( CONTROL N Figure 9-2 ...
Page 90
... A break is defined as the transmission or reception of a low (logic 0) for at least one complete frame time. IDLE LINE START Figure 9-3. Data Format Serial Communications Interface (SCI) is used and must meet the CONTROL BIT M SELECTS 8- OR 9-BIT DATA STOP START MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 91
... MSB of the first character of each message and leave it clear for all other characters in the message. Idle periods may be present within messages and no idle time is required between messages for this wakeup method. MC68HC705C9A — Rev. 4.0 MOTOROLA Serial Communications Interface (SCI) Serial Communications Interface (SCI) Idle Line Wakeup Advance Information ...
Page 92
... The value of the bit is determined by voting logic which takes 1RT 2RT START START START SAMPLES 8RT 9RT 10RT Serial Communications Interface (SCI) Figure 9-6. 3RT 4RT 5RT 6RT 7RT NOISE NEXT BIT 16RT 1RT MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 93
... MC68HC705C9A — Rev. 4.0 MOTOROLA 9-4 least two of these three verification samples detect a Figure DATA ...
Page 94
... Figure 9-8. SCI Data Register (SCDR) Serial Communications Interface (SCI) DETECTED AS VALID START EDGE START BIT START START EDGE QUALIFIERS VERIFICATION SAMPLES 9-3. The transmitter generates a bit Figure 9-8, is the buffer for BIT3 BIT2 BIT1 MC68HC705C9A — Rev. 4.0 MOTOROLA 9.7 Bit 0 BIT0 ...
Page 95
... The ninth bit can be used as an extra stop bit receiver wakeup signal mark or space parity bit. Resets have no effect on the M bit. MC68HC705C9A — Rev. 4.0 MOTOROLA Stores ninth SCI data bit received and ninth SCI data bit transmitted Controls SCI character length ...
Page 96
... Enables SCI wakeup Transmits SCI break characters Bit TIE TCIE RIE ILIE Figure 9-10. SCI Control Register 2 (SCCR2 TDRE interrupt requests enabled 0 = TDRE interrupt requests disabled Serial Communications Interface (SCI) Figure 9-10, has these Bit RWU SBK MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 97
... Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver and receiver interrupts but does not affect the receiver interrupt flags. Resets clear the RE bit. MC68HC705C9A — Rev. 4.0 MOTOROLA interrupt requests enabled interrupt requests disabled 1 = RDRF interrupt requests enabled ...
Page 98
... Break codes being transmitted break codes being transmitted Transfer of SCDR data to transmit shift register complete Transmission complete Transfer of receive shift register data SCDR complete Receiver input idle Noisy data Framing error Serial Communications Interface (SCI) Figure 9-11, contains flags to MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 99
... This clearable, read-only flag is set when the data in the receive shift register transfers to the SCI data register. RDRF generates an interrupt request if the RIE bit in the SCCR2 is also set. Clear the RDRF bit by reading the SCSR with RDRF set and then reading the SCDR. MC68HC705C9A — Rev. 4.0 MOTOROLA Bit TDRE TC ...
Page 100
... FE bit by reading the SCSR and then reading the SCDR. Advance Information 100 1 = Receiver input idle 0 = Receiver input not idle 1 = Receive shift register full and RDRF = receiver overrun 1 = Noise detected in SCDR noise detected in SCDR 1 = Framing error framing error Serial Communications Interface (SCI) MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 101
... The baud rate register (BAUD), shown in rate for both the receiver and the transmitter. $000D Read: Write: Reset: SCP1 — SCP0–SCI Prescaler Select Bits These read/write bits control prescaling of the baud rate generator clock, as shown in MC68HC705C9A — Rev. 4.0 MOTOROLA Bit SCP1 SCP0 — — 0 ...
Page 102
... Table 9-2. Baud Rate Selection SCR[2:0] SCI Baud Rate (Baud) 000 Prescaled Clock 001 Prescaled Clock 010 Prescaled Clock 011 Prescaled Clock 100 Prescaled Clock 101 Prescaled Clock 110 Prescaled Clock 111 Prescaled Clock Serial Communications Interface (SCI 128 MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 103
... An SPI system may be configured in one containing one master MCU and several slave MCUs system in which an MCU is capable of being a master or a slave. MC68HC705C9A — Rev. 4.0 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Master In Slave Out (MISO 105 Master Out Slave In (MOSI) ...
Page 104
... Bus frequency divided by 2 (maximum) master bit frequency Bus frequency (maximum) slave bit frequency Four programmable master bit rates Programmable clock polarity and phase End of transmission interrupt flag Write collision flag protection Master-master mode fault protection capability Serial Peripheral Interface (SPI) MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 105
... Master Out Slave In (MOSI) The MOSI line is configured as an output in a master device and as an input in a slave device one of the two lines that transfer serial data in one direction with the most significant bit sent first. MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 106
... When CPHA = 1, SS may be left low for several SPI characters. In cases where there is only one SPI slave MCU, its SS line could be tied to V Advance Information 106 Figure 10-1, four possible timing relationships may be as long as CPHA = 1 clock modes are used. SS Serial Peripheral Interface (SPI) MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 107
... SPR1 SPR0 SPI CONTROL REGISTER (SPCR) SPI STATUS REGISTER (SPSR) SPI DATA REGISTER (SPDR) Figure 10-2. Serial Peripheral Interface Block Diagram MC68HC705C9A — Rev. 4.0 MOTOROLA shows a block diagram of the serial peripheral interface SPI SHIFT REGISTER SPDR ($000C) SPIE SPE MSTR ...
Page 108
... MOSI, MISO, SCK, and SS master-slave PD3/MOSI SPI SHIFT REGISTER PD2/MISO PD5/SS I/O PORT SPDR ($000C) PD4/SCK MASTER MCU Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection Serial Peripheral Interface (SPI) SPI SHIFT REGISTER SPDR ($000C) SLAVE MCU MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 109
... Reset: SPIE — Serial Peripheral Interrupt Enable Bit This read/write bit enables SPI interrupts. Reset clears the SPIE bit. MC68HC705C9A — Rev. 4.0 MOTOROLA Enables SPI interrupts Enables the SPI system Selects between standard CMOS or open drain outputs for port D (C9A mode only) ...
Page 110
... See Advance Information 110 1 = SPI system enabled 0 = SPI system disabled 1 = Port D outputs act as open-drain outputs Port D outputs are normal CMOS outputs Master mode 0 = Slave mode Figure 10-1. Serial Peripheral Interface (SPI) Figure 10-1. MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 111
... If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated. Clearing the SPIF bit is accomplished by reading the SPSR (with MC68HC705C9A — Rev. 4.0 MOTOROLA Table 10-1. They have no effect in the slave mode. Table 10-1. SPI Clock ...
Page 112
... MODF bit has been cleared. When configured as an MC68HC05C9A also necessary to restore DDRD after a mode fault. Bits 5 and 3–0 — Not Implemented These bits always read 0. Advance Information 112 mode. Serial Peripheral Interface (SPI) MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 113
... In cases of overrun, the byte which causes the overrun is lost. A write to the serial peripheral data I/O register is not buffered and places data directly into the shift register for transmission. $000C Read: Write: Reset: MC68HC705C9A — Rev. 4.0 MOTOROLA Bit SPD7 SPD6 SPD5 SPD4 Unaffected by reset Figure 10-6 ...
Page 114
... Serial Peripheral Interface (SPI) Advance Information 114 Serial Peripheral Interface (SPI) MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 115
... The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is MC68HC705C9A — Rev. 4.0 MOTOROLA Section 11. Instruction Set Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Immediate ...
Page 116
... The opcode is the first byte, and the immediate data value is the second byte. Advance Information 116 Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative Instruction Set MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 117
... The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. ...
Page 118
... When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. ...
Page 119
... These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. MC68HC705C9A — Rev. 4.0 MOTOROLA Register/memory instructions Read-modify-write instructions Jump/branch instructions Bit manipulation instructions Control instructions Table 11-1 ...
Page 120
... Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value. Instruction Set Mnemonic ASL ASR (1) BCLR (1) BSET CLR COM DEC INC LSL LSR NEG ROL ROR (2) TST MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 121
... The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. MC68HC705C9A — Rev. 4.0 MOTOROLA Instruction Set Instruction Set Instruction Types Advance Information ...
Page 122
... Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine Instruction Set Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 123
... CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. 11.4.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. MC68HC705C9A — Rev. 4.0 MOTOROLA Table 11-4. Bit Manipulation Instructions Instruction Bit Clear Branch if Bit Clear Branch if Bit Set Bit Set Table 11-5 ...
Page 124
... IX1 IMM DIR EXT IX2 IX1 IMM DIR EXT — IX2 IX1 DIR 38 5 INH INH 58 3 IX1 DIR 37 5 INH INH 57 3 IX1 REL DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 REL REL REL REL REL REL MOTOROLA ...
Page 125
... BRSET n opr rel Branch if Bit n Set BSET n opr Set Bit n BSR rel Branch to Subroutine CLC Clear Carry Bit CLI Clear Interrupt Mask MC68HC705C9A — Rev. 4.0 MOTOROLA Description (PC rel ? IRQ = 1 — — — — — PC (PC rel ? IRQ = 0 — — — — — (A) (M) — ...
Page 126
... DIR EXT IX2 IX1 DIR 33 5 INH INH 53 3 IX1 IMM DIR EXT IX2 IX1 DIR 3A 5 INH — INH 5A 3 IX1 IMM DIR EXT — IX2 IX1 DIR 3C 5 INH — INH 5C 3 IX1 DIR EXT IX2 IX1 MOTOROLA ...
Page 127
... Logical OR Accumulator with Memory ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX Rotate Byte Left through Carry Bit ROL opr,X ROL ,X MC68HC705C9A — Rev. 4.0 MOTOROLA Description (PC Push (PCL); SP (SP) – 1 — — — — — Push (PCH); SP (SP) – ...
Page 128
... Instruction Set CCR dd DIR 36 5 INH INH 56 3 IX1 INH 9C 2 INH 80 9 INH IMM DIR EXT IX2 IX1 INH 99 2 INH DIR EXT — IX2 IX1 INH DIR EXT — IX2 IX1 IMM DIR EXT IX2 IX1 INH 83 10 MOTOROLA ...
Page 129
... Inherent addressing mode IX Indexed, no offset addressing mode IX1 Indexed, 8-bit offset addressing mode IX2 Indexed, 16-bit offset addressing mode M Memory location N Negative flag n Any bit 11.6 Opcode Map See MC68HC705C9A — Rev. 4.0 MOTOROLA Description X (M) – $00 A opr PC PCH PCL REL rel – ...
Page 130
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...
Page 131
... Serial Peripheral Interface Timing . . . . . . . . . . . . . . . 142 12.11 3.3- Vdc Serial Peirpheral Interface Timing . . . . . . . . . . . . . . 143 MC68HC705C9A — Rev. 4.0 MOTOROLA Section 12. Electrical Specifications Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Power Considerations 133 5.0-Vdc Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 135 3 ...
Page 132
... Connect unused inputs to the appropriate In Out Rating Symbol and 12.6 5.0-Vdc Electrical Characteristics Characteristic Electrical Specifications and V within the range Out Value V –0 –0 0 –0 0 –65 to +150 STG for Symbol Value T –40 to +85 A MC68HC705C9A — Rev. 4.0 MOTOROLA Unit Unit C ...
Page 133
... For most applications P The following is an approximate relationship between P (neglecting P Solving equations (1) and (2) for K gives: where constant pertaining to the particular part. K can be determined from equation (3) by measuring P known T by solving equations (1) and (2) iteratively for any value of T MC68HC705C9A — Rev. 4.0 MOTOROLA Characteristic ...
Page 134
... V DD Pins R1 PA7–PA0 PB7–PB0 3.26 2.38 PC7–PC0 PD5–PD0, PD7 Pins R1 PA7–PA0 PB7–PB0 10.91 6.32 PC7–PC0 PD5–PD0, PD7 Figure 12-1. Test Load Electrical Specifications R2 SEE TABLE R1 (SEE TABLE MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 135
... loads; less than all outputs the OSC2 capacitance. 5. Stop I measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port –0 Input pullup current measured with V MC68HC705C9A — Rev. 4.0 MOTOROLA (1) Symbol 2.1 MHz –40 to +85 C, unless otherwise noted A –0 loads; less than all outputs 0.2 V. ...
Page 136
... SS DD — 1.0 1.6 — 500 900 — 1.0 8 — 2.5 20 — — 10 — — 1 0.5 — 20 — — 12 — — OSC2 L , all other inputs OSC2. Wait I is affected linearly all other inputs MC68HC705C9A — Rev. 4.0 MOTOROLA Unit all DD ...
Page 137
... DD 5. – 4.00 mA 3.00 mA 2.00 mA 1.00 mA Figure 12-2. Maximum Supply Current vs Internal Clock Frequency, V Figure 12-3. Maximum Supply Current vs Internal Clock Frequency, V MC68HC705C9A — Rev. 4.0 MOTOROLA 50 A 0.5 MHz 1.0 MHz 1.5 MHz INTERNAL CLOCK FREQUENCY (XTAL 3 – ...
Page 138
... DC 2.1 480 — — 100 — 100 1.5 — 4.0 — 125 — TL (3) — 125 — (4) — 90 — ), this is the limiting minimum factor CYC MC68HC705C9A — Rev. 4.0 MOTOROLA Unit MHz MHz CYC t CYC ns t CYC ns t CYC ns ...
Page 139
... ILIL routine plus CYC TCAP PIN * Refer to timer resolution data in Figure 12-4. TCAP Timing Relationships MC68HC705C9A — Rev. 4.0 MOTOROLA ( Vdc –40 to +85 C, unless otherwise noted A . CYC t * TLTL 12 ...
Page 140
... ILIL t ILIH should not be less than the number of t ILIL cycles. CYC t ILIH 4064 t CYC 3FFE 3FFE 3FFE Electrical Specifications ) is either 125 2.1 MHz) ILIH OP cycles it takes to CYC 3FFE 3FFE 3FFF4 RESET OR INTERRUPT VECTOR FETCH MC68HC705C9A — Rev. 4.0 MOTOROLA ...
Page 141
... RESET Notes: 1. Internal clock, internal address bus, and internal data bus are not available externally. 2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence. MC68HC705C9A — Rev. 4.0 MOTOROLA 4064 t CYC 3FFE 3FFE 3FFE ...
Page 142
... M t 100 — 120 A t — 240 DIS t t 0.25 — — 240 ( ) 0.25 — — — 100 RM t — 2 — 100 FM t — 2.0 FS Figure 12-9 and Figure 12-10. MC68HC705C9A — Rev. 4.0 MOTOROLA Unit f OP MHz t CYC CYC CYC ...
Page 143
... DD 13 SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS 3.3 Vdc 0.3 Vdc Vdc Signal production depends on software. 3. Assumes 200 pF load on all SPI pins. MC68HC705C9A — Rev. 4.0 MOTOROLA (1) ( 200 pF 200 pF –40 to +85 C, unless otherwise noted. Refer to A ...
Page 144
... MSB IN BIT 6–1 11 MASTER MSB OUT BIT 6–1 a) SPI Master Timing (CPHA = MSB IN BIT 6–1 11 BIT 6–1 b) SPI Master Timing (CPHA = 1) Electrical Specifications LSB (ref) MASTER LSB OUT 12 12 NOTE 13 NOTE 6 7 LSB MASTER LSB OUT 12 MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO NOTE (OUTPUT) MOSI (INPUT) Note: Not defined but normally LSB of character previously transmitted. Figure 12-10. SPI Slave Timing Diagram MC68HC705C9A — Rev. 4.0 MOTOROLA MSB OUT BIT 6– BIT 6–1 a) SPI Slave Timing (CPHA = 0) ...
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... Electrical Specifications Advance Information 146 Electrical Specifications MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... Plastic Shrink Dual In-Line (SDIP) Package (Case 858-01 148 44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02 149 44-Lead Quad Flat Pack (QFP) (Case 824A-01 150 Local Motorola Sales Office World Wide Web at http://www.motorola.com/semiconductors Mechanical Specifications Advance Information 147 ...
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... D 0.014 0.022 0.36 0.56 F 0.032 0.046 0.81 1.17 G 0.070 BSC 1.778 BSC H 0.300 BSC 7.62 BSC J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L 0.600 BSC 15.24 BSC 0.020 0.040 0.51 1.02 S MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... PROTUSION(S) SHALL NOT CAUSE THE H DIMINSION TO BE GREATER THAN 0.037 (0.940150). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMINISION TO SMALLER THAN 0.025 (0.635). Figure 13-3. 44-Lead PLCC (Case 777-02) MC68HC705C9A — Rev. 4.0 MOTOROLA 44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02 BRK -M- W ...
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... REF 0.13 0.17 0.005 0.13 0.30 0.005 S 12.95 13.45 0.510 T 0.13 0.005 12.95 13.45 0.510 W 0.40 0.016 X 1.6 REF 0.063 REF MC68HC705C9A — Rev. 4.0 MOTOROLA MAX 0.398 0.398 0.096 0.018 0.083 0.016 0.010 0.009 0.037 10 0.007 7 0.012 0.530 0.530 ...
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... P = Plastic dual in-line package (PDIP Shrink dual in-line package (SDIP Plastic-leaded chip carrier (PLCC Quad flat pack (QFP) MC68HC705C9A — Rev. 4.0 MOTOROLA Section 14. Ordering Information Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 shows the MC order numbers for the available package Table 14-1. MC Order Numbers ...
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... Ordering Information Advance Information 152 Ordering Information MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... EPROM, but it may be done from a host. The user code must be a one-to-one correspondence with the internal EPROM addresses. MC68HC705C9A — Rev. 4.0 MOTOROLA Appendix A. EPROM Programming Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Programming Register (PROG) ...
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... Address and data buses latched when the following instruction is a write the EPROM locations. Normal reading is disabled if LATCH = EPROM address and data bus configured for normal reading EPROM Programming PD3 Mode 0 Program/verify 1 Verify only 0 Load RAM and execute X Secure LATCH MC68HC705C9A — Rev. 4.0 MOTOROLA Bit 0 EPGM 0 ...
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... LATCH cannot be set in the single write. NOTE: Bits 7–3 and bit 1 MUST be set to 0 when writing to the EPROM programming register. MC68HC705C9A — Rev. 4.0 MOTOROLA 1 = Programming voltage applied to EPROM array 0 = Programming voltage not applied to EPROM array EPROM Programming EPROM Programming Programming Register (PROG) ...
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... EPROM Programming Advance Information 156 EPROM Programming MC68HC705C9A — Rev. 4.0 MOTOROLA ...
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... Advance Information — MC68HC705C9A Appendix B. M68HC05Cx Family Feature Comparisons Refer to M68HC05C Family members. MC68HC705C9A — Rev. 4.0 MOTOROLA Table B-1 for a comparison of the features for all the M68HC05Cx Family Feature Comparisons Advance Information 157 ...
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C4 C4A 705C4A C8 USER ROM 4160 4160 — 7744 USER EPROM — — 4160 — CODE NO YES YES NO SECURITY RAM 176 176 176 176 OPTION REGISTER $1FDF (IRQ/RAM/ (IRQ/SEC) SEC) MASK OPTION NO NO ...
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...
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... Motorola was negligent regarding the design or manufacture of the part. Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners ...