MC68HC705J1A Motorola, MC68HC705J1A Datasheet

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... M68HC05 Microcontrollers WWW.MOTOROLA.COM/SEMICONDUCTORS MC68HC705J1A MC68HRC705J1A MC68HSC705J1A MC68HSR705J1A Technical Data MC68HC705J1A/D Rev. 4, 5/2002 ...

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... For your convenience, the page number designators have been linked to the appropriate location. Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. digital dna is a trademark of Motorola, Inc. MC68HC705J1A — Rev. 4.0 MOTOROLA © Motorola, Inc., 2002 Technical Data ...

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... Figure 2-4. Mask Option Register (MOR) May, 2002 4.0 state 6.3.3 Pulldown Register A 6.4.3 Pulldown Register B Technical Data 4 Revision History Description — Corrected reset state for — Corrected reset — Corrected note — Corrected note Page Number( MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... Section 9. Multifunction Timer Module . . . . . . . . . . . . . 109 Section 10. Electrical Specifications 117 Section 11. Mechanical Specifications . . . . . . . . . . . . . 131 Section 12. Ordering Information . . . . . . . . . . . . . . . . . 135 Appendix A. MC68HRC705J1A . . . . . . . . . . . . . . . . . . . 137 Appendix B. MC68HSC705J1A . . . . . . . . . . . . . . . . . . . 141 Appendix C. MC68HSR705J1A . . . . . . . . . . . . . . . . . . . 145 Index 151 MC68HC705J1A — Rev. 4.0 MOTOROLA (COP) Module . . . . . . . . . . . . . . . . . . . . . . . . . 97 List of Sections List of Sections Technical Data 5 ...

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... List of Sections Technical Data 6 List of Sections MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... MC68HC705J1A — Rev. 4.0 MOTOROLA Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Programmable Options Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V and OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . . 28 RC Oscillator ...

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... Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Instruction Set .52 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . 55 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . 56 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .57 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . 59 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table of Contents MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... MC68HC705J1A — Rev. 4.0 MOTOROLA Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Section 4. Resets and Interrupts Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Resets Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Interrupts Software Interrupt ...

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... I/O Port Electrical Characteristics . . . . . . . . . . . . . . . . 95 Section 7. Computer Operating Properly (COP) Module Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 COP Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 COP Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . . 98 Clearing the COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . .98 Interrupts COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Table of Contents MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... MC68HC705J1A — Rev. 4.0 MOTOROLA Section 8. External Interrupt Module (IRQ) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 IRQ/V Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 PP Optional External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 104 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 106 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5 ...

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... Section 12. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Appendix A. MC68HRC705J1A Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Typical Internal Operating Frequency for RC Oscillator Option 139 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . 140 Table of Contents MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... B.4 B.5 B.6 C.1 C.2 C.3 C.4 C.5 C.6 C.7 MC68HC705J1A — Rev. 4.0 MOTOROLA Appendix B. MC68HSC705J1A Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.0-Volt DC Electrical Characteristics .142 3.3-Volt DC Electrical Characteristics .142 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . 144 Appendix C. MC68HSR705J1A Contents ...

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... Table of Contents Technical Data 14 Table of Contents MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... MC68HC705J1A — Rev. 4.0 MOTOROLA Title Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin Assignments .26 Bypassing Layout Recommendation . . . . . . . . . . . . . . . . . . 26 Crystal Connections with Oscillator Internal Resistor Mask Option . . . . . . . . . . . . . 28 Crystal Connections without Oscillator Internal Resistor Mask Option . . . . . . . . . . . . . 28 Ceramic Resonator Connections with Oscillator Internal Resistor Mask Option ...

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... Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 IRQ Status and Control Register (ISCR 106 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Multifunction Timer Block Diagram .110 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Timer Status and Control Register (TSCR 112 Timer Counter Register (TCR 114 List of Figures Page MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... A-1 A-2 B-1 B-2 C-1 C-2 C-3 MC68HC705J1A — Rev. 4.0 MOTOROLA Title PA0–PA7, PB0–PB5 Typical High-Side Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 123 PA0–PA3, PB0–PB5 Typical Low-Side Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 123 PA4–PA7 Typical Low-Side Driver Characteristics . . . . . . 124 Typical Operating I (25 C) ...

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... List of Figures Technical Data 18 List of Figures MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... A-1 B-1 C-1 MC68HC705J1A — Rev. 4.0 MOTOROLA Title Programmable Options Register/Memory Instructions Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . 56 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .58 Bit Manipulation Instructions Control Instructions Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ...

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... List of Tables Technical Data 20 List of Tables MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... Contents 1.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.2.1 1.5.2.2 1.5.2.3 1.5.2.4 1.6 1.7 1.8 1.9 MC68HC705J1A — Rev. 4.0 MOTOROLA Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Programmable Options Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V and OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . . 28 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 External Clock ...

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... The MC68HRC705J1A is a resistor-capacitor (RC) oscillator mask option version of the MC68HC705J1A and is discussed in MC68HRC705J1A. A high-speed version of the MC68HC705J1A, the MC68HSC705J1A, is discussed in The MC68HSR705J1A, discussed high-speed version of the MC68HRC705J1A. A functional block diagram of the MC68HC705J1A is shown in Figure Technical Data 22 Appendix B. MC68HSC705J1A. 1-1. General Description Appendix A ...

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... OSC1 INTERNAL OSCILLATOR OSC2 RESET IRQ/V PP MC68HC705J1A — Rev. 4.0 MOTOROLA 15-STAGE DIVIDE MULTIFUNCTION BY ³2 TIMER SYSTEM WATCHDOG AND ILLEGAL ADDRESS DETECT CPU CONTROL ALU 68HC05 CPU ACCUMULATOR CPU REGISTERS INDEX REGISTER STK PTR PROGRAM COUNTER CONDITION CODE REGISTER STATIC RAM (SRAM) — 64 BYTES USER EPROM — ...

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... General Description 1.3 Features Features of the MC68HC705J1A include: • • • • • • • • • • • • Technical Data 24 Peripheral modules: – 15-stage multifunction timer – Computer operating properly (COP) watchdog 14 bidirectional input/output (I/O) lines, including: – 10-mA sink capability on four I/O pins – ...

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... Edge-sensitive only or edge- and level-sensitive Enabled or disabled Enabled or disabled Stop mode or halt mode Enabled or disabled Enabled or disabled Enabled or disabled shows the MC68HC705J1A pin assignments. and V are the power supply and ground pins. The MCU operates SS Figure 1-3 General Description General Description ...

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... General Description Technical Data 26 OSC1 1 OSC2 2 PB5 3 PB4 4 PB3 5 PB2 6 PB1 7 PB0 Figure 1-2. Pin Assignments MCU C2 0 Figure 1-3. Bypassing Layout Recommendation General Description 20 RESET 19 IRQ PA0 17 PA1 16 PA2 15 PA3 14 PA4 13 PA5 12 PA6 PA7 MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... To minimize output distortion, mount the crystal and capacitors as close as possible to the pins. An internal startup resistor of approximately programmable mask option. NOTE: Use an AT-cut crystal and not an AT-strip crystal because the MCU can overdrive an AT-strip crystal. MC68HC705J1A — Rev. 4.0 MOTOROLA Figure 1-4 and Figure 1-6 MC68HRC705J1A and Appendix C ...

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... Figure 1-4. Crystal Connections with Oscillator Internal Resistor Mask Option MCU R 10 M¾ XTAL Figure 1-5. Crystal Connections without Oscillator Internal Resistor Mask Option Figure 1-6 and Figure 1-7 General Description OSC1 XTAL OSC2 OSC1 XTAL R OSC2 show ceramic resonator MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... Mount the resonator and components as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup resistor of approximately provided between OSC1 and OSC2 as a programmable mask option. MC68HC705J1A — Rev. 4.0 MOTOROLA MCU CERAMIC RESONATOR Figure 1-6. Ceramic Resonator Connections ...

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... EXTERNAL CMOS CLOCK Figure 1-8. External Clock Connections pulls the RESET pin high. A steering diode between the RESET DD pins discharges any RESET pin voltage when power is DD for more information. General Description and Appendix C. MCU Section 4. MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... These eight input/output (I/O) lines comprise port A, a general-purpose, bidirectional I/O port. See for information on PA0–PA3 external interrupts. 1.9 PB0–PB5 These six I/O lines comprise port B, a general-purpose, bidirectional I/O port. MC68HC705J1A — Rev. 4.0 MOTOROLA and Section 8. External Interrupt Module for wired-OR operation. If the IRQ/V DD ...

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... General Description Technical Data 32 General Description MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... Introduction This section describes the organization of the on-chip memory consisting of: • • MC68HC705J1A — Rev. 4.0 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Memory Map Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . . .35 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . . 38 EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . 39 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 EPROM Programming Characteristics ...

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... Unimplemented $000F $0010 $0011 $0012 Unimplemented $0017 $0018 $0019 Unimplemented $001E Reserved $001F (1) $07F0 $07F1 $07F2 Reserved $07F7 $07F8 $07F9 $07FA $07FB $07FC $07FD Reset Vector High $07FE Reset Vector Low $07FF MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... See page 93. Reset: $0006 Unimplemented $0007 Unimplemented Read: Timer Status and Control $0008 Register (TSCR) Write: See page 112. Reset: Figure 2-2. I/O Register Summary (Sheet MC68HC705J1A — Rev. 4.0 MOTOROLA Bit PA7 PA6 PA5 PA4 Unaffected by reset 0 0 PB5 PB4 ...

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... Figure 2-2. I/O Register Summary (Sheet Technical Data 36 Bit TMR7 TMR6 TMR5 TMR4 IRQE PDIA7 PDIA6 PDIA5 PDIA4 PDIB5 PDIB4 Unimplemented R = Reserved Memory Bit 0 TMR3 TMR2 TMR1 TMR0 IRQF IRQR PDIA3 PDIA2 PDIA1 PDIA0 PDIB3 PDIB2 PDIB1 PDIB0 ELAT MPGM EPGM MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... CPU retrieves a byte from the stack. NOTE: Be careful when using nested subroutines or multiple interrupt levels. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. MC68HC705J1A — Rev. 4.0 MOTOROLA Bit ...

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... Manipulating the control bits in the EPROM programming register 2. Programming the EPROM/OTPROM with the M68HC705J Technical Data 38 $0300–$07CF $07F8–$07FF, used for user-defined interrupt and reset vectors to program the EPROM/OTPROM on a byte-by-byte basis in-circuit simulator (M68HC705JICS) available from Motorola Memory MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... Reset clears MPGM. EPGM — EPROM Programming Bit This read/write bit applies the voltage from the IRQ/V EPROM. To write the EPGM bit, the ELAT bit must be set already. Reset clears EPGM. MC68HC705J1A — Rev. 4.0 MOTOROLA $0018 Bit 7 6 ...

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... Port A external interrupts (enable or disable) Port pulldown resistors (enable or disable) STOP instruction (stop mode or halt mode) Crystal oscillator internal resistor (enable or disable) EPROM security (enable or disable) Short oscillator delay (enable or disable) Memory , to the IRQ/V pin EPGM MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... EPMSEC — EPROM Security Bit The EPMSEC bit controls access to the EPROM/OTPROM. OSCRES — Oscillator Internal Resistor Bit The OSCRES bit enables a 2-M circuit. NOTE: Program the OSCRES bit to logic 0 in devices using RC oscillators. MC68HC705J1A — Rev. 4.0 MOTOROLA $07F1 Bit SOSCD ...

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... PA0–PA3 enabled as external interrupt pins 0 = PA0–PA3 not enabled as external interrupt pins 1 = External interrupts triggered by active edges and active levels 0 = External interrupts triggered only by active edges 1 = COP watchdog enabled 0 = COP watchdog disabled Memory occurs after cyc MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... EPROM Programming Characteristics Programming voltage IRQ/V Programming current IRQ/V Programming time Per array byte MOR 1. V MC68HC705J1A — Rev. 4.0 MOTOROLA (1) Characteristic 5.0 Vdc 10 Vdc Memory EPROM Programming Characteristics Symbol Min Typ V 16.0 16 —¦ 3 EPGM 4 — t MPGM 4 — = – +105 C ...

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... Memory Technical Data 44 MC68HC705J1A — Rev. 4.0 Memory MOTOROLA ...

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... MC68HC705J1A — Rev. 4.0 MOTOROLA Section 3. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Arithmetic/Logic Unit CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Instruction Set .52 Addressing Modes ...

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... Condition code register (CCR) with five status flags 62 instructions Eight addressing modes Power-saving stop, wait, halt, and data-retention modes Central Processor Unit (CPU) Figure 3-1. MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... CPU CONTROL UNIT CARRY/BORROW FLAG MC68HC705J1A — Rev. 4.0 MOTOROLA HALF-CARRY FLAG INTERRUPT MASK NEGATIVE FLAG ZERO FLAG Figure 3-1. Programming Model Central Processor Unit (CPU) Central Processor Unit (CPU) Arithmetic/Logic Unit ARITHMETIC/LOGIC UNIT 1 0 ACCUMULATOR ( INDEX REGISTER ( STACK POINTER (SP) ...

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... Read: Write: Reset: Technical Data 48 Accumulator Index register Stack pointer Program counter Condition code register Bit Unaffected by reset Figure 3-2. Accumulator (A) Bit Unaffected by reset Figure 3-3. Index Register (X) Central Processor Unit (CPU Bit Bit 0 MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... If subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00FF and begins writing over the previously stored data. A subroutine uses two stack locations; an interrupt uses five locations. MC68HC705J1A — Rev. 4.0 MOTOROLA Bit 15 14 ...

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... Read: Write: Reset: Technical Data 50 Bit Loaded with vector from $07FE and $07FF Figure 3-5. Program Counter (PC) Bit Unimplemented Figure 3-6. Condition Code Register (CCR) Central Processor Unit (CPU Unaffected MC68HC705J1A — Rev. 4.0 MOTOROLA Bit 1 0 Bit ...

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... The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some logical operations and data manipulation instructions also clear or set the carry/borrow flag. MC68HC705J1A — Rev. 4.0 MOTOROLA Central Processor Unit (CPU) Central Processor Unit (CPU) ...

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... The opcode is the first byte, and the immediate data value is the second byte. Technical Data 52 Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative Central Processor Unit (CPU) MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). MC68HC705J1A — Rev. 4.0 MOTOROLA Central Processor Unit (CPU) ...

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... When using the Motorola assembler, the programmer does not need to calculate the offset because the assembler determines the proper offset and verifies that it is within the span of the branch. Technical Data 54 Central Processor Unit (CPU) MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. MC68HC705J1A — Rev. 4.0 MOTOROLA Register/memory instructions Read-modify-write instructions Jump/branch instructions ...

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... BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value. Central Processor Unit (CPU) Mnemonic ASL ASR (1) BCLR (1) BSET CLR COM DEC INC LSL LSR NEG ROL ROR (2) TST MC68HC705J1A — Rev. 4.0 MOTOROLA ...

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... The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. NOTE: Do not use BRCLR or BRSET instructions on registers with write-only bits. MC68HC705J1A — Rev. 4.0 MOTOROLA Central Processor Unit (CPU) Central Processor Unit (CPU) Instruction Set Technical Data ...

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... Branch if bit set Branch to subroutine Unconditional jump Jump to subroutine Central Processor Unit (CPU) Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 59

... I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. NOTE: Do not use bit manipulation instructions on registers with write-only bits. MC68HC705J1A — Rev. 4.0 MOTOROLA Table 3-4. Bit Manipulation Instructions Instruction Bit clear ...

Page 60

... Stop oscillator and enable IRQ pin Software interrupt Transfer accumulator to index register Transfer index register to accumulator Stop CPU clock and enable interrupts Central Processor Unit (CPU) Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 61

... Branch if Carry Bit Clear BCLR n opr Clear Bit n BCS rel Branch if Carry Bit Set (Same as BLO) BEQ rel Branch if Equal BHCC rel Branch if Half-Carry Bit Clear BHCS rel Branch if Half-Carry Bit Set MC68HC705J1A — Rev. 4.0 MOTOROLA Description A (A) + (M) + (C) A (A) + (M) A (A) (M) C ...

Page 62

... DIR (b4 DIR (b5 DIR (b6 DIR (b7 — — — — — REL DIR (b0 DIR (b1 DIR (b2 DIR (b3 — — — — DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 — — — — — DIR (b4 DIR (b5 DIR (b6 DIR (b7 MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 63

... EOR #opr EOR opr EOR opr EXCLUSIVE OR Accumulator with Memory Byte EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX Increment Byte INC opr,X INC ,X MC68HC705J1A — Rev. 4.0 MOTOROLA Description PC (PC push (PCL) SP (SP) – 1; push (PCH) SP (SP) – (PC) + rel C 0 ...

Page 64

... IX1 DIR 34 5 INH — — 0 INH 54 3 IX1 — — — 0 INH DIR 30 5 INH — — INH 50 3 IX1 — — — — — INH IMM DIR EXT — — — IX2 IX1 MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 65

... STX opr STX opr STX opr,X Store Index Register In Memory STX opr,X STX ,X SUB #opr SUB opr SUB opr Subtract Memory Byte from Accumulator SUB opr,X SUB opr,X SUB ,X MC68HC705J1A — Rev. 4.0 MOTOROLA Description $00FF SP (SP Pull (CCR) SP (SP Pull (A) SP (SP ...

Page 66

... Relative program counter offset byte rr Relative program counter offset byte SP Stack pointer X Index register Z Zero flag # Immediate value Logical AND Logical OR Logical EXCLUSIVE Contents of –( ) Negation (two’s complement) Loaded with ? If : Concatenated with  Set or cleared — Not affected MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 67

Bit Manipulation Branch DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR BRCLR0 BCLR0 ...

Page 68

... Central Processor Unit (CPU) Technical Data 68 Central Processor Unit (CPU) MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 69

... Reset initializes the microcontroller unit (MCU) by returning the program counter to a known address and by forcing control and status bits to known states. Interrupts temporarily change the sequence of program execution to respond to events that occur during processing. MC68HC705J1A — Rev. 4.0 MOTOROLA Section 4. Resets and Interrupts Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Resets Power-On Reset ...

Page 70

... Power-on reset (POR) circuit RESET pin Computer operating properly (COP) watchdog Illegal address ILLEGAL ADDRESS COP WATCHDOG POWER-ON RESET V DD INTERNAL CLOCK Figure 4-1. Reset Sources Resets and Interrupts TO CPU AND RST S PERIPHERAL D Q MODULES CK RESET LATCH MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 71

... ADDRESS BUS Notes: 1. Power-on reset threshold is typically between 1 V and Internal clock, internal address bus, and internal data bus are not available externally. MC68HC705J1A — Rev. 4.0 MOTOROLA DD (internal clock cycle) delay after the oscillator becomes cyc ...

Page 72

... RESET Figure 4-3. External Reset Timing Table 4-1. External Reset Timing Characteristic Resets and Interrupts generates an external cyc $07FE $07FF NEW PC NEW PC NEW NEW OP DUMMY PCH PCL CODE Symbol Min Max Unit t t 1.5 — RL cyc MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 73

... When the CPU completes its current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition code register. If the I bit is clear, the CPU then begins the interrupt sequence. MC68HC705J1A — Rev. 4.0 MOTOROLA Software interrupt (SWI) instruction External interrupt pins: – ...

Page 74

... PP Figure 4-5, is latched as long as any source Resets and Interrupts pin can latch another interrupt PP pin interrupt logic BIH & BIL INSTRUCTION PROCESSING IRQF EXTERNAL IRQ Q INTERRUPT REQUEST IRQE CLR MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 75

... IRQ (INTERNAL) Interrupt pulse width low (edge-triggered) Interrupt pulse period The minimum, t Interrupt pulse width low (edge-triggered) Interrupt pulse period The minimum, t MC68HC705J1A — Rev. 4.0 MOTOROLA t ILIL t ILIH t ILIH Figure 4-5. External Interrupt Timing Table 4-2. External Interrupt Timing (V Characteristic = 5 ...

Page 76

... Loads the program counter with the contents of the appropriate interrupt vector locations: – $07FC and $07FD (software interrupt vector) – $07FA and $07FB (external interrupt vector) – $07F8 and $07F9 (timer interrupt vector) Resets and Interrupts Figure 4-6. MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 77

... STACKING Function Reset Software interrupt (SWI) External interrupt Timer interrupts 1. The COP watchdog is programmable in the mask option register. MC68HC705J1A — Rev. 4.0 MOTOROLA UNSTACKING ORDER 5 1 CONDITION CODE REGISTER PROGRAM COUNTER (HIGH BYTE PROGRAM COUNTER (LOW BYTE) ORDER Figure 4-6. Interrupt Stacking Order Table 4-4 ...

Page 78

... EXTERNAL INTERRUPT? NO TIMER YES INTERRUPT? STACK PC CCR NO LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES INSTRUCTION? UNSTACK CCR EXECUTE INSTRUCTION Figure 4-7. Interrupt Flowchart Resets and Interrupts CLEAR IRQ LATCH SET I BIT MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 79

... Introduction The microcontroller unit (MCU) can enter these low-power standby modes: • • • MC68HC705J1A — Rev. 4.0 MOTOROLA Section 5. Low-Power Modes Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Exiting Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Effects of Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . .81 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Timer ...

Page 80

... External interrupt — A high-to-low transition on the IRQ/V a low-to-high transition on an enabled port A external interrupt pin starts the CPU clock and loads the program counter with the contents of locations $07FA and $07FB. Low-Power Modes voltages as low DD pin or PP pin or PP MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 81

... The WAIT instruction disables the CPU clock. After exiting wait mode, the CPU clock and all enabled peripheral clocks immediately begin running. MC68HC705J1A — Rev. 4.0 MOTOROLA COP watchdog reset — A timeout of the COP watchdog resets the MCU, starts the CPU clock, and loads the program counter with the contents of locations $07FE and $07FF ...

Page 82

... Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts Disables the CPU clock Clears the interrupt mask (I bit) in the condition code register, enabling interrupts Disables the CPU clock Clears the COP watchdog counter Disables the COP watchdog clock Low-Power Modes MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 83

... After exiting stop mode by reset and after the oscillator stabilization delay, the timer resumes operation from its reset state. The WAIT instruction: The WAIT instruction has no effect on the timer. MC68HC705J1A — Rev. 4.0 MOTOROLA The COP watchdog counter immediately begins counting from $0000. ...

Page 84

... Lower the V To take the MCU out of data-retention mode: 1. Return V 2. Return the RESET pin to logic 1. Technical Data 84 voltage. The RESET pin must remain low DD continuously during data-retention mode. to normal operating voltage. DD Low-Power Modes voltages as low as 2.0 Vdc. DD MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 85

... BUS Notes: 1. Internal clocking from OSC1 pin 2. Edge-triggered external interrupt mask option 3. Edge- and level-triggered external interrupt mask option 4. Reset vector shown as example Figure 5-1. Stop Mode Recovery Timing MC68HC705J1A — Rev. 4.0 MOTOROLA OSCILLATOR STABILIZATION DELAY $07FE $07FE $07FE $07FE ...

Page 86

... LOAD PC WITH INTERRUPT VECTOR Figure 5-2. Stop/Halt/Wait Flowchart Low-Power Modes WAIT CLEAR I BIT IN CCR SET IRQE BIT IN ISCR TURN OFF CPU CLOCK TIMER CLOCK ACTIVE YES EXTERNAL RESET? NO YES EXTERNAL INTERRUPT? NO YES TIMER INTERRUPT? NO YES COP RESET? NO MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 87

... NOTE: Connect any unused I/O pins to an appropriate logic level, either V V SS. operation, termination reduces excess current consumption and the possibility of electrostatic damage. MC68HC705J1A — Rev. 4.0 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Port Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Data Direction Register Pulldown Register Port A LED Drive Capability . . . . . . . . . . . . . . . . . . . . . . . . . 92 Port A I/O Pin Interrupts ...

Page 88

... PDIA7 PDIA6 PDIA5 PDIA4 PDIB5 PDIB4 Unimplemented Parallel Input/Output (I/O) Ports Bit 0 PA3 PA2 PA1 PA0 PB3 PB2 PB1 PB0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 PDIA3 PDIA2 PDIA1 PDIA0 PDIB3 PDIB2 PDIB1 PDIB0 MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 89

... Read: Write: Reset: PA[7:0] — Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. MC68HC705J1A — Rev. 4.0 MOTOROLA $0000 Bit PA7 ...

Page 90

... PAx READ PORTA WRITE PDRA PDRAx RESET Figure 6-4. Port A I/O Circuitry Parallel Input/Output (I/O) Ports Bit 0 DDRA3 DDRA2 DDRA1 DDRA0 10-mA SINK CAPABILITY (PINS PA4–PA7 ONLY) PAx (PA0–PA3 TO IRQ MODULE) 100- A PULLDOWN SWPDI MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 91

... A pins as inputs with disabled pulldown devices. Address: Read: Write: Reset: PDIA[7:0] — Pulldown Inhibit A Bits PDIA[7:0] disable the port A pulldown devices. Reset clears PDIA[7:0]. MC68HC705J1A — Rev. 4.0 MOTOROLA Table 6-1. Port A Pin Operation I/O Pin Mode 0 Input, high-impedance 1 Output ...

Page 92

... B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. Technical Data (IRQ). $0001 Bit PB5 PB4 Unaffected by reset = Unimplemented Figure 6-6. Port B Data Register (PORTB) Parallel Input/Output (I/O) Ports Section Bit 0 PB3 PB2 PB1 PB0 MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 93

... These read/write bits control port B data direction. Reset clears DDRB[5:0], configuring all port B pins as inputs. NOTE: Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from Figure 6-8 MC68HC705J1A — Rev. 4.0 MOTOROLA $0005 Bit ...

Page 94

... Figure 6-9. Pulldown Register B (PDRB Corresponding port B pulldown device disabled 0 = Corresponding port B pulldown device not disabled Parallel Input/Output (I/O) Ports Table 6-2 summarizes the operation Accesses to Data Bit Read Write Pin Latch Latch Latch PDIB3 PDIB2 PDIB1 MC68HC705J1A — Rev. 4.0 MOTOROLA (1) Bit 0 PDIB0 0 ...

Page 95

... I/O ports hi-z leakage current PA0–PA7, PB0–PB5 (without individual pulldown activated) Input pulldown current PA0–PA7, PB0–PB5 (with individual pulldown activated 3.3 Vdc 10 Vdc Typical values reflect average measurements at midpoint of voltage range MC68HC705J1A — Rev. 4.0 MOTOROLA (1) Symbol ...

Page 96

... Parallel Input/Output (I/O) Ports Technical Data 96 Parallel Input/Output (I/O) Ports MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 97

... COP watchdog and prevents COP reset. The COP watchdog function is programmable by the COPEN bit in the mask option register. Features include: • • MC68HC705J1A — Rev. 4.0 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 COP Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 COP Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . . 98 Clearing the COP Watchdog ...

Page 98

... To clear the COP watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the COP register at location $07F0 (see Technical Data 98 and V . Periodically clearing the counter starts SS DD Computer Operating Properly (COP) Module PP Module. Figure 7-1). MC68HC705J1A — Rev. 4.0 MOTOROLA pin ...

Page 99

... The COP register (COPR write-only register that returns the contents of EPROM location $07F0 when read. Address: Read: Write: Reset: COPC — COP Clear Bit This write-only bit resets the COP watchdog. Reading address $07F0 returns undefined results. MC68HC705J1A — Rev. 4.0 MOTOROLA pin voltage. PP $07F0 Bit Unimplemented Figure 7-1 ...

Page 100

... The counter is cleared again after the oscillator stabilization delay and begins counting from $0000 again. The counter begins counting from $0000. The counter is not cleared again after the oscillator stabilization delay and continues counting throughout the oscillator stabilization delay. Computer Operating Properly (COP) Module MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 101

... The external interrupt (IRQ) module provides asynchronous external interrupts to the CPU. These sources can generate external interrupts: • • Features include: • • • MC68HC705J1A — Rev. 4.0 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 IRQ/V Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 PP Optional External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 104 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 106 External Interrupt Timing ...

Page 102

... IRQ module. LEVEL-SENSITIVE TRIGGER (MOR LEVEL BIT IRQ D Q LATCH CK CLR RESET IRQ VECTOR FETCH IRQR External Interrupt Module (IRQ) ) and port A PP Figure 8-2 TO BIH & BIL INSTRUCTION PROCESSING IRQF EXTERNAL INTERRUPT REQUEST IRQE MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 103

... MC68HC705J1A — Rev. 4.0 MOTOROLA FROM RESET YES I BIT SET? NO YES EXTERNAL INTERRUPT? NO TIMER YES INTERRUPT? STACK PCL, PCH CCR NO LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES UNSTACK CCR PCH, PCL INSTRUCTION? NO Figure 8-2. Interrupt Flowchart ...

Page 104

... PP pin contains an internal Schmitt trigger as part of its input PP pin except for the inverted phase (logic 1, rising edge). The PP pin is a logic 0 (falling edge). PP External Interrupt Module (IRQ) input requires an PP pin is not MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 105

... The IRQ pin has an internal Schmitt trigger. The optional external interrupts (PA0–PA3) do not have internal Schmitt triggers. The interrupt mask bit (I) in the condition code register (CCR) disables all maskable interrupt requests, including external interrupt requests. MC68HC705J1A — Rev. 4.0 MOTOROLA External Interrupt Module (IRQ) External Interrupt Module (IRQ) ...

Page 106

... Clears external interrupt and IRQF bit effect on external interrupt and IRQF bit 1 = External interrupt request pending external interrupt request pending 1 = External interrupt requests enabled 0 = External interrupt requests disabled External Interrupt Module (IRQ Bit 0 IRQF IRQR Reserved MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 107

... The minimum should not be less than the number of interrupt service routine cycles plus 19 ILIL MC68HC705J1A — Rev. 4.0 MOTOROLA t ILIL t ILIH t ILIH Figure 8-4. External Interrupt Timing (1) = – +105 C unless otherwise noted A (1) = – +105 C, unless otherwise noted ...

Page 108

... External Interrupt Module (IRQ) Technical Data 108 External Interrupt Module (IRQ) MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 109

... The multifunction timer provides a timing reference with programmable real-time interrupt (RTI) capability. organization. Features include: • • • MC68HC705J1A — Rev. 4.0 MOTOROLA Section 9. Multifunction Timer Module Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Interrupts 112 I/O Registers 112 Timer Status and Control Register . . . . . . . . . . . . . . . . . . .112 Timer Counter Register ...

Page 110

... Figure 9-1. Multifunction Timer Block Diagram Technical Data 110 TIMER COUNTER REGISTER BITS [0:7] OF 15-STAGE RIPPLE COUNTER RESET TIMER STATUS/CONTROL REGISTER RTI RATE SELECT BITS [8:14] OF 15-STAGE RIPPLE COUNTER Multifunction Timer Module RESET INTERNAL CLOCK 4 (XTAL 2) INTERRUPT REQUEST RESET COP RESET Q MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 111

... RT0 bits in the timer status and control register at address $0008 allow a timer interrupt every 16,384, 32,768, 65,536, or 131,072 clock cycles. The last four stages drive the selectable COP system. For information on the COP, refer to the Properly (COP) MC68HC705J1A — Rev. 4.0 MOTOROLA Bit ...

Page 112

... Flags timer interrupts Enables timer interrupts Resets timer interrupt flags Selects real-time interrupt rates $0008 Bit TOF RTIF TOIE RTIE Unimplemented Figure 9-3. Timer Status and Control Register (TSCR) Multifunction Timer Module Bit RT1 RT0 TOFR RTIFR MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 113

... COP watchdog. Reset sets RT1 and RT0. NOTE: Changing RT1 and RT0 when a COP timeout is imminent can cause a real-time interrupt request to be missed or an additional real-time MC68HC705J1A — Rev. 4.0 MOTOROLA 1 = Timer overflow interrupts enabled 0 = Timer overflow interrupts disabled ...

Page 114

... Bit TMR7 TMR6 TMR5 TMR4 Unimplemented Figure 9-4. Timer Counter Register (TCR) Multifunction Timer Module Number COP Timeout of Cycles (1) Period to COP Reset 17 65 131,072 18 131 262,144 19 262 524,288 20 524 1,048,576 TMR3 TMR2 TMR1 MC68HC705J1A — Rev. 4.0 MOTOROLA (1) Bit 0 TMR0 0 ...

Page 115

... Wait Mode The timer remains active after a WAIT instruction. Any enabled timer interrupt request can bring the MCU out of wait mode. MC68HC705J1A — Rev. 4.0 MOTOROLA Clears the timer counter Clears interrupt flags (TOF and RTIF) and interrupt enable bits (TOFE and RTIE) in TSCR, removing any pending timer interrupt requests and disabling further timer interrupts ...

Page 116

... Multifunction Timer Module Technical Data 116 Multifunction Timer Module MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 117

... Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.11 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . 126 10.12 5.0-Volt Control Timing 10.13 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.2 Introduction This section contains electrical and timing specifications. MC68HC705J1A — Rev. 4.0 MOTOROLA Section 10. Electrical Specifications Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Operating Temperature Range 119 Thermal Characteristics ...

Page 118

... Connect unused inputs to the appropriate In Out (1) Symbol Rating , V , and PA4–PA7 pin 10.7 5.0-Volt DC Electrical Characteristics Electrical Specifications and V within the range Out Value V –0 – – –65 to +150 STG and for guaranteed operating MC68HC705J1A — Rev. 4.0 MOTOROLA Unit ...

Page 119

... DW = small outline integrated circuit (SOIC ceramic DIP (cerdip extended temperature range automotive temperature range 10.5 Thermal Characteristics Thermal resistance plastic dual in-line package (PDIP small outline integrated circuit (SOIC ceramic DIP (cerdip) MC68HC705J1A — Rev. 4.0 MOTOROLA Package Type (1) (2) ( (4) P, CDW, CS ...

Page 120

... I/O < P I/O INT , the relationship between P I 273 273 Using this value of K, the values Electrical Specifications , in C can be obtained from and can be neglected. and T is approximately (at equilibrium) for a D and T can be obtained MC68HC705J1A — Rev. 4.0 MOTOROLA (1) (2) (3) ...

Page 121

... MHz); all inputs 0.2 V from rail loads; less than all outputs; C osc 5. Stop mode I is measured with OSC1 = – 0 Only input high current rated RESET. 7. The R value selected for RC oscillator versions of this device is unspecified. See osc additional information. MC68HC705J1A — Rev. 4.0 MOTOROLA (1) Symbol RESET, OSC1 , RESET, OSC1 – ...

Page 122

... MHz); all inputs 0.2 V from rail loads; is measured using external square wave OSC2 Appendix C. MC68HSR705J1A MC68HC705J1A — Rev. 4.0 MOTOROLA Unit 0.2 V; for ...

Page 123

... Notes 5.0 V, devices are specified and tested for 3.3 V, devices are specified and tested for V DD Figure 10-2. PA0–PA3, PB0–PB5 Typical Low-Side Driver Characteristics MC68HC705J1A — Rev. 4.0 MOTOROLA 800 mV 700 mV 600 mV 500 mV 400 mV 300 mV 200 5.0 V ...

Page 124

... V, devices are specified and tested for 3.3 V, devices are specified and tested for V DD Figure 10-3. PA4–PA7 Typical Low-Side Driver Characteristics Technical Data 124 800 mV 700 mV 600 mV 500 mV 400 mV 300 mV 200 5 100 400 300 Electrical Specifications 10.0 mA 5.0 mA. OL MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 125

... Typical Supply Currents Notes: Notes: MC68HC705J1A — Rev. 4.0 MOTOROLA 6.0 mA 5.0 mA 4.0 mA 3.0 mA 2 INTERNAL OPERATING FREQUENCY ( 5.0 V, devices are specified and tested for 3.3 V, devices are specified and tested for I DD Figure 10-4. Typical Operating I 700 A 600 A ...

Page 126

... RL t 1.5 — ILIH (2) t 1.5 Note ILIL t 1.5 — IHIL (2) t 1.5 Note IHIH 200 — MC68HC705J1A — Rev. 4.0 MOTOROLA Unit Unit MHz MHz ns t cyc t cyc t cyc t cyc t cyc ns ...

Page 127

... SS 2. The maximum width ILIL ILIH routine plus the interrupt service routine will be re-entered. cyc MC68HC705J1A — Rev. 4.0 MOTOROLA ( – +105 C, unless otherwise noted A , should not be more than the number of cycles it takes to execute the interrupt service Electrical Specifications Electrical Specifications 3 ...

Page 128

... Edge- and level-triggered external interrupt mask option 4. Reset vector shown as example Figure 10-7. Stop Mode Recovery Timing Technical Data 128 t ILIL t ILIH t ILIH 4064 t cyc 07FE 07FE 07FE (NOTE 4) Electrical Specifications 07FE 07FE 07FF RESET OR INTERRUPT VECTOR FETCH MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 129

... DATA BUS Notes : 1. Internal clock, internal address bus, and internal data bus are not available externally. 2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence. MC68HC705J1A — Rev. 4.0 MOTOROLA 4064 t cyc 07FE 07FE 07FE Figure 10-8 ...

Page 130

... Electrical Specifications Technical Data 130 Electrical Specifications MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 131

... Technical Data — MC68HC705J1A 11.1 Contents 11.2 11.3 11.4 11.5 11.2 Introduction The MC68HC705J1A, the resistor-capacitor (RC) oscillator, and high-speed option devices described in MC68HRC705J1A, MC68HSR705J1A • • • MC68HC705J1A — Rev. 4.0 MOTOROLA Section 11. Mechanical Specifications Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Plastic Dual In-Line Package (Case 738 132 Small Outline Integrated Circuit (Case 751) ...

Page 132

... C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 X 45 1.27 BSC 0.050 BSC G J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 MC68HC705J1A — Rev. 4.0 MOTOROLA 7 ...

Page 133

... Ceramic Dual In-Line Package (Case 732 SEATING PLANE MC68HC705J1A — Rev. 4.0 MOTOROLA Mechanical Specifications Mechanical Specifications Ceramic Dual In-Line Package (Case 732) NOTES: 1. LEADS WITHIN 0.010 DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL ...

Page 134

... Mechanical Specifications Technical Data 134 Mechanical Specifications MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 135

... Technical Data — MC68HC705J1A 12.1 Contents 12.2 12.3 12.2 Introduction This section contains ordering information for the available package types. 12.3 MCU Order Numbers Table 12-1 Package SOIC Cerdip 1. Refer Plastic dual in-line package (PDIP Extended temperature range Automotive temperature range 5 ...

Page 136

... Ordering Information Technical Data 136 Ordering Information MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 137

... A.2 A.3 A.4 A.5 A.2 Introduction This appendix introduces the MC68HRC705J1A, a resistor-capacitor (RC) oscillator mask option version of the MC68HC705J1A. All of the information in this document applies to the MC68HRC705J1A with the exceptions given in this appendix. MC68HC705J1A — Rev. 4.0 MOTOROLA Appendix A. MC68HRC705J1A Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 RC Oscillator Connections ...

Page 138

... Technical Data 138 Figure A-1 to drive the on-chip oscillator. Mount R MCU Figure A-1. RC Oscillator Connections MC68HRC705J1A OSC1 OSC2 Figure A-1. For such MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 139

... Figure A-2. Typical Internal Operating Frequency for Various V MC68HC705J1A — Rev. 4.0 MOTOROLA Typical Internal Operating Frequency for RC Oscillator Option shows typical internal operating frequencies for the 100 1000 RESISTANCE ( — RC Oscillator Option Only DD MC68HRC705J1A MC68HRC705J1A 3 ...

Page 140

... C –40 to +105 751D-04 20 –40 to +85 C –40 to +105 732-03 20 –40 to +85 C –40 to +105 C Section 12. Ordering Information for standard part ordering information. MC68HRC705J1A (1) Order Number (2) MC68HRC705J1AP (3) MC68HRC705J1AC P (4) MC68HRC705J1AV P (5) MC68HRC705J1ADW MC68HRC705J1ACDW MC68HRC705J1AVDW (6) MC68HRC705J1AS MC68HRC705J1ACS MC68HRC705J1AVS MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 141

... B.3 B.4 B.5 B.6 B.2 Introduction This appendix introduces the MC68HSC705J1A, a high-speed version of the MC68HC705J1A. All of the information in this document applies to the MC68HSC705J1A with the exceptions given in this appendix. MC68HC705J1A — Rev. 4.0 MOTOROLA Appendix B. MC68HSC705J1A Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.0-Volt DC Electrical Characteristics .142 3 ...

Page 142

... DD OP Figure B-1. Typical High-Speed Operating I MC68HSC705J1A Min Typ Max Unit I — 4.25 7.0 DD 0.57 3.25 Min Typ Max Unit I — 1.4 4.25 DD 0.28 1.75 SEE NOTE 1 5.5 V 4.5 V 3.6 V 3.0 V 3.0 MHz 4.0 MHz ) OP ( MC68HC705J1A — Rev. 4.0 MOTOROLA mA mA ...

Page 143

... MC68HC705J1A — Rev. 4.0 MOTOROLA 700 A 600 A 500 A 400 A 300 A 200 A 100 1.0 MHz INTERNAL OPERATING FREQUENCY (f Notes 5.0 V, high-speed devices are specified and tested for 4.0 MHz 3.3 V, high-speed devices are specified and tested for 2.1 MHz Figure B-2. Typical High-Speed Wait Mode I ...

Page 144

... Table B-1. MC68HSC705J1A (High Speed) Order Numbers Case Pin Operating Outline Count Temperature 738-03 20 –40 to +85 C 751D-04 20 –40 to +85 C 732-03 20 –40 to +85 C Section 12. Ordering Information MC68HSC705J1A Order Number MC68HSC705J1AP MC68HSC705J1AC MC68HSC705J1ADW MC68HSC705J1ACDW MC68HSC705J1AS MC68HSC705J1ACS for standard part ordering information. MC68HC705J1A — Rev. 4.0 MOTOROLA (1) (2) (3) P (4) (5) ...

Page 145

... MC68HRC705J1A. All of the information in this document applies to the MC68HSR705J1A with the exceptions given in this appendix. C.3 RC Oscillator Connections (External Resistor) Refer to resistor-capacitor (RC) oscillator connections with external resistor. MC68HC705J1A — Rev. 4.0 MOTOROLA Appendix C. MC68HSR705J1A Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 RC Oscillator Connections (External Resistor 145 Typical Internal Operating Frequency for High-Speed RC Oscillator Option ...

Page 146

... Technical Data 146 RESISTANCE (k ) Figure C-1. Typical Internal Operating Frequency for High-Speed RC Oscillator Option MC68HSR705J1A 3.0 V 3.6 V 4.5 V 5 100 Appendix A. MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 147

... When programming the OSCRES bit for the MC68HSR705J1A, an internal resistor is selected which yields typical internal oscillator frequencies as shown in device is different than the resistance of the selectable internal resistor on the MC68HC705J1A and the MC68HSC705J1A devices. NOTE: This option is not available on the ROM version of this device (MC68HC05J1A). ...

Page 148

... However, this data is not guaranteed the user’s responsibility to ensure that the resulting internal operating frequency meets the user’s requirements. Technical Data 148 50 100 TEMPERATURE ( C) MC68HSR705J1A 3.0 V 3.6 V 4.5 V 5.0 V 5.5 V 150 MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 149

... C.7 Package Types and Order Numbers Package SOIC Cerdip 1. Refer plastic dual in-line package (PDIP extended temperature range small outline integrated circuit (SOIC ceramic dual in-line package (cerdip) MC68HC705J1A — Rev. 4.0 MOTOROLA Table C-1 MC68HSR705J1A (High-Speed . RC Oscillator Option) Order Numbers Case Pin Type ...

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... MC68HSR705J1A Technical Data 150 MC68HSR705J1A MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 151

... COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPEN bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC705J1A — Rev. 4.0 MOTOROLA COP in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP register (COPR COP reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 152

... EPGM bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EPMSEC bit EPROM EPROM security programmable option . . . . . . . . . . . . . . . . . . . . EPROM/OTPROM erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38, programming characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . programming register (EPROG Technical Data 152 D E MC68HC705J1A — Rev. 4.0 Index 117 127 122 123 118 142 145 ...

Page 153

... I bit index register ( instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . instruction types interrupts MC68HC705J1A — Rev. 4.0 MOTOROLA addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 154

... STOP instruction flowchart stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, stop recovery timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timing of stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . wait mode Technical Data 154 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31, 98 Index 112 76 73 104 106 106 106 120 115 85 79 MC68HC705J1A — Rev. 4.0 MOTOROLA ...

Page 155

... MC68HSR705J1A (high-speed RC oscillator option mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPGM bit multifunction timer module bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC705J1A — Rev. 4.0 MOTOROLA programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 156

... I/O circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O pin interrupts (PA0–PA3 LED drive capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pins pulldown register (PDRA port B data direction register (DDRB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Data 156 O P MC68HC705J1A — Rev. 4.0 Index 135 140 144 149 149 ...

Page 157

... RAM registers RESET pin 30, resets resistors (pulldown) RT1, RT0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC705J1A — Rev. 4.0 MOTOROLA I/O circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pins port B data register (PORTB pulldown register (PDRB programmable option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 158

... TOF bit TOFR bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TOIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Data 158 S T MC68HC705J1A — Rev. 4.0 Index 113 113 113 105 41 49 106 100 100 115 86 85 ...

Page 159

... WAIT instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81, 100, wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC705J1A — Rev. 4.0 MOTOROLA pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin effects on timer Index Technical Data Index 25 25 106 100 115 51 159 ...

Page 160

... Index Technical Data 160 MC68HC705J1A — Rev. 4.0 Index MOTOROLA ...

Page 161

...

Page 162

... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2002 MC68HC705J1A/D ...