MC68HC705J1A Motorola, MC68HC705J1A Datasheet - Page 102

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MC68HC705J1A

Manufacturer Part Number
MC68HC705J1A
Description
Manufacturer
Motorola
Datasheet

Specifications of MC68HC705J1A

Case
DIP-20L
External Interrupt Module (IRQ)
8.3 Operation
The interrupt request/programming voltage pin (IRQ/V
pins 0–3 (PA0–PA3) provide external interrupts. The PIRQ bit in the
mask option register (MOR) enables PA0–PA3 as IRQ interrupt sources,
which are combined into a single ORing function to be latched by the
IRQ latch.
After completing its current instruction, the CPU tests the IRQ latch. If the
IRQ latch is set, the CPU then tests the I bit in the condition code register
and the IRQE bit in the IRQ status and control register. If the
I bit is clear and the IRQE bit is set, the CPU then begins the interrupt
sequence. This interrupt is serviced by the interrupt service routine
located at $07FA and $07FB.
The CPU clears the IRQ latch while it fetches the interrupt vector, so that
another external interrupt request can be latched during the interrupt
service routine. As soon as the I bit is cleared during the return from
interrupt, the CPU can recognize the new interrupt request.
shows the sequence of events caused by an interrupt.
IRQ
PA3
PA2
PA1
PA0
PIRQ
(MOR)
Figure 8-1. IRQ Module Block Diagram
Technical Data
102
Figure 8-1
shows the structure of the IRQ module.
LEVEL-SENSITIVE TRIGGER
(MOR LEVEL BIT)
V
DD
IRQ
D
Q
LATCH
CK
CLR
RESET
IRQ VECTOR FETCH
IRQR
External Interrupt Module (IRQ)
) and port A
PP
Figure 8-2
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQF
EXTERNAL
INTERRUPT
REQUEST
IRQE
MC68HC705J1A — Rev. 4.0
MOTOROLA

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