MC68HC705J1A Motorola, MC68HC705J1A Datasheet - Page 105

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MC68HC705J1A

Manufacturer Part Number
MC68HC705J1A
Description
Manufacturer
Motorola
Datasheet

Specifications of MC68HC705J1A

Case
DIP-20L
If edge- and level-sensitive triggering is selected, a rising edge or a high
level on a PA0–PA3 pin latches an external interrupt request. Edge- and
level-sensitive triggering allows the use of multiple wired-OR external
interrupt sources. As long as any source is holding a PA0–PA3 pin high,
an external interrupt request is latched, and the CPU continues to
execute the interrupt service routine.
If edge-sensitive only triggering is selected, a rising edge on a PA0–PA3
pin latches an external interrupt request. A subsequent external interrupt
request can be latched only after the voltage level of the previous
interrupt signal returns to logic 0 and then rises again to logic 1.
NOTE:
The branch if interrupt pin is high (BIH) and branch if interrupt pin is low
(BIL) instructions apply only to the level on the IRQ/V
to the output of the logic OR function with the PA0–PA3 pins. The state
of the individual port A pins can be checked by reading the appropriate
port A pins as inputs.
Enabled PA0–PA3 pins cause an IRQ interrupt regardless of whether
these pins are configured as inputs or outputs.
The IRQ pin has an internal Schmitt trigger. The optional external
interrupts (PA0–PA3) do not have internal Schmitt triggers.
The interrupt mask bit (I) in the condition code register (CCR) disables
all maskable interrupt requests, including external interrupt requests.
MC68HC705J1A — Rev. 4.0
MOTOROLA
External Interrupt Module (IRQ)
External Interrupt Module (IRQ)
Operation
pin itself and not
PP
Technical Data
105

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