MC68HC705J1A Motorola, MC68HC705J1A Datasheet - Page 106

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MC68HC705J1A

Manufacturer Part Number
MC68HC705J1A
Description
Manufacturer
Motorola
Datasheet

Specifications of MC68HC705J1A

Case
DIP-20L
External Interrupt Module (IRQ)
8.4 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. All unused bits in the ISCR read as
logic 0s. The IRQF bit is cleared and the IRQE bit is set by reset.
Address:
Read:
Write:
Reset:
IRQR — Interrupt Request Reset Bit
This write-only bit clears the external interrupt request flag.
IRQF — External Interrupt Request Flag
The external interrupt request flag is a clearable, read-only bit that is
set when an external interrupt request is pending. Reset clears the
IRQF bit.
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Reset sets the IRQE
bit.
The STOP and WAIT instructions set the IRQE bit so that an external
interrupt can bring the MCU out of these low-power modes. In addition,
reset sets the I bit which masks all interrupt sources.
Technical Data
106
$000A
Bit 7
6
5
4
0
0
0
IRQE
R
1
0
0
0
= Unimplemented
Figure 8-3. IRQ Status and Control Register (ISCR)
1 = Clears external interrupt and IRQF bit
0 = No effect on external interrupt and IRQF bit
1 = External interrupt request pending
0 = No external interrupt request pending
1 = External interrupt requests enabled
0 = External interrupt requests disabled
External Interrupt Module (IRQ)
3
2
1
Bit 0
IRQF
0
0
0
IRQR
0
0
0
0
R = Reserved
MC68HC705J1A — Rev. 4.0
MOTOROLA

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