MC68HC705J1A

Manufacturer Part NumberMC68HC705J1A
ManufacturerMotorola
MC68HC705J1A datasheet
 

Specifications of MC68HC705J1A

CaseDIP-20L  
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Page 111/162

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Addr.
Register Name
Read:
Timer Status and Control
$0008
Register (TSCR)
Write:
See page 112.
Reset:
Read:
Timer Counter Register
(TCR)
$0009
Write:
See page 114.
Reset:
9.3 Operation
A 15-stage ripple counter, preceded by a prescaler that divides the
internal clock signal by four, provides the timing reference for the timer
functions. The value of the first eight timer stages can be read at any
time by accessing the timer counter register at address $0009. A timer
overflow function at the eighth stage allows a timer interrupt every 1024
internal clock cycles.
The next four stages lead to the real-time interrupt (RTI) circuit. The RT1
and RT0 bits in the timer status and control register at address $0008
allow a timer interrupt every 16,384, 32,768, 65,536, or 131,072 clock
cycles. The last four stages drive the selectable COP system. For
information on the COP, refer to the
Properly (COP)
MC68HC705J1A — Rev. 4.0
MOTOROLA
Bit 7
6
5
TOF
RTIF
TOIE
0
0
0
TMR7
TMR6
TMR5
TMR4
0
0
0
= Unimplemented
Figure 9-2. I/O Register Summary
Module.
Multifunction Timer Module
Multifunction Timer Module
4
3
2
1
0
0
RTIE
RT1
TOFR
RTIFR
0
0
0
1
TMR3
TMR2
TMR1
0
0
0
0
Section 7. Computer Operating
Technical Data
Operation
Bit 0
RT0
1
TMR0
0
111