MC68HC705J1A

Manufacturer Part NumberMC68HC705J1A
ManufacturerMotorola
MC68HC705J1A datasheet
 


Specifications of MC68HC705J1A

CaseDIP-20L  
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Page 114/162:

Multifunction Timer Module

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Multifunction Timer Module

interrupt request to be generated. To prevent this occurrence, clear the
COP timer before changing RT1 and RT0.
RT1:RT0
1. At 2-MHz bus, 4-MHz XTAL, 0.5 s per cycle
9.5.2 Timer Counter Register
A 15-stage ripple counter is the core of the timer. The value of the first
eight stages is readable at any time from the read-only timer counter
register (TCR) shown in
Address:
Read:
Write:
Reset:
Power-on clears the entire counter chain and the internal clock begins
clocking the counter. After 4064 cycles (or 16 cycles if the SOSCD bit in
the mask option register is set), the power-on reset circuit is released,
clearing the counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage allows a timer
interrupt every 1024 internal clock cycles.
Technical Data
114
Table 9-1. Real-Time Interrupt Rate Selection
Number
RTI
of Cycles
Period
to RTI
14
0 0
8.2 ms
2
= 16,384
15
0 1
16.4 ms
2
= 32,768
16
1 0
32.8 ms
2
= 65,536
17
1 1
65.5 ms
2
= 131,072
Figure
9-4.
$0009
Bit 7
6
5
TMR7
TMR6
TMR5
TMR4
0
0
0
= Unimplemented
Figure 9-4. Timer Counter Register (TCR)

Multifunction Timer Module

Number
COP Timeout
of Cycles
(1)
Period
to COP Reset
17
65.5 ms
2
= 131,072
18
131.1 ms
2
= 262,144
19
262.1 ms
2
= 524,288
20
524.3 ms
2
= 1,048,576
4
3
2
1
TMR3
TMR2
TMR1
0
0
0
0
MC68HC705J1A — Rev. 4.0
MOTOROLA
(1)
Bit 0
TMR0
0