MC68HC705J1A

Manufacturer Part NumberMC68HC705J1A
ManufacturerMotorola
MC68HC705J1A datasheet
 


Specifications of MC68HC705J1A

CaseDIP-20L  
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Memory
SWAIT — Stop-to-Wait Conversion Bit
The SWAIT bit enables halt mode. When the SWAIT bit is set, the
CPU interprets the STOP instruction as a WAIT instruction, and the
MCU enters halt mode. Halt mode is the same as wait mode, except
that an oscillator stabilization delay of 1 to 4064 t
exiting halt mode.
SWPDI — Software Pulldown Inhibit Bit
The SWPDI bit inhibits software control of the I/O port pulldown
devices. The SWPDI bit overrides the pulldown inhibit bits in the port
pulldown inhibit registers.
PIRQ — Port A External Interrupt Bit
The PIRQ bit enables the PA0–PA3 pins to function as external
interrupt pins.
LEVEL —External Interrupt Sensitivity Bit
The LEVEL bit controls external interrupt triggering sensitivity.
COPEN — COP Enable Bit
The COPEN bit enables the COP watchdog.
Technical Data
42
1 = Halt mode enabled
0 = Halt mode not enabled
1 = Software pulldown control inhibited
0 = Software pulldown control not inhibited
1 = PA0–PA3 enabled as external interrupt pins
0 = PA0–PA3 not enabled as external interrupt pins
1 = External interrupts triggered by active edges and active levels
0 = External interrupts triggered only by active edges
1 = COP watchdog enabled
0 = COP watchdog disabled
Memory
occurs after
cyc
MC68HC705J1A — Rev. 4.0
MOTOROLA