MC68HC705J1A Motorola, MC68HC705J1A Datasheet - Page 51

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MC68HC705J1A

Manufacturer Part Number
MC68HC705J1A
Description
Manufacturer
Motorola
Datasheet

Specifications of MC68HC705J1A

Case
DIP-20L
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an ADD (add without carry) or ADC
(add with carry) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations.
I — Interrupt Mask Bit
Setting the interrupt mask disables interrupts. If an interrupt request
occurs while the interrupt mask is logic 0, the CPU saves the CPU
registers on the stack, sets the interrupt mask, and then fetches the
interrupt vector. If an interrupt request occurs while the interrupt mask
is logic 1, the interrupt request is latched. Normally, the CPU
processes the latched interrupt request as soon as the interrupt mask
is cleared again.
A return-from-interrupt instruction (RTI) unstacks the CPU registers,
restoring the interrupt mask to its cleared state. After any reset, the
interrupt mask is set and can be cleared only by a software
instruction.
N — Negative Flag
The CPU sets the negative flag when an ALU operation produces a
negative result.
Z — Zero Flag
The CPU sets the zero flag when an ALU operation produces a result
of $00.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow flag.
MC68HC705J1A — Rev. 4.0
MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
CPU Registers
Technical Data
51

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