MC68HC705J1A

Manufacturer Part NumberMC68HC705J1A
ManufacturerMotorola
MC68HC705J1A datasheet
 


Specifications of MC68HC705J1A

CaseDIP-20L  
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Instruction Set

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Central Processor Unit (CPU)
3.6 Instruction Set
The MCU instruction set has 62 instructions and uses eight addressing
modes.
3.6.1 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
3.6.1.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
3.6.1.2 Immediate
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
Technical Data
52
Inherent
Immediate
Direct
Extended
Indexed, no offset
Indexed, 8-bit offset
Indexed, 16-bit offset
Relative
Central Processor Unit (CPU)
MC68HC705J1A — Rev. 4.0
MOTOROLA