MC68HC705J1A Motorola, MC68HC705J1A Datasheet - Page 63

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MC68HC705J1A

Manufacturer Part Number
MC68HC705J1A
Description
Manufacturer
Motorola
Datasheet

Specifications of MC68HC705J1A

Case
DIP-20L
Table 3-6. Instruction Set Summary (Sheet 3 of 6)
Source
Operation
Form
BSR rel
Branch to Subroutine
CLC
Clear Carry Bit
CLI
Clear Interrupt Mask
CLR opr
CLRA
CLRX
Clear Byte
CLR opr,X
CLR ,X
CMP #opr
CMP opr
CMP opr
Compare Accumulator with Memory Byte
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
Complement Byte (One’s Complement)
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
Compare Index Register with Memory Byte
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
Decrement Byte
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EXCLUSIVE OR Accumulator with Memory Byte
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
Increment Byte
INC opr,X
INC ,X
MC68HC705J1A — Rev. 4.0
MOTOROLA
Description
PC
(PC) + 2; push (PCL)
SP
(SP) – 1; push (PCH)
SP
(SP) – 1
PC
(PC) + rel
C
0
I
0
M
$00
A
$00
X
$00
M
$00
M
$00
(A) – (M)
M
M
(
) = $FF – (M)
A
A
(
) = $FF – (A)
X
X
(
) = $FF – (X)
M
M
(
) = $FF – (M)
M
M
(
) = $FF – (M)
(X) – (M)
M
(M) – 1
A
(A) – 1
X
(X) – 1
M
(M) – 1
M
(M) – 1
A
(A)
(M)
M
(M) + 1
A
(A) + 1
X
(X) + 1
M
(M) + 1
M
(M) + 1
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Instruction Set Summary
Effect
on CCR
H I N Z C
— — — — —
REL
AD
rr
6
— — — — 0
INH
98
2
— 0 — — —
INH
9A
2
dd
DIR
3F
5
INH
4F
3
— — 0 1 —
INH
5F
3
IX1
6F
6
ff
IX
7F
5
ii
IMM
A1
2
dd
DIR
B1
3
hh ll
  
EXT
C1
4
— —
ee ff
IX2
D1
5
ff
IX1
E1
4
IX
F1
3
dd
DIR
33
5
INH
43
3
 
— —
1
INH
53
3
IX1
63
6
ff
IX
73
5
ii
IMM
A3
2
dd
DIR
B3
3
hh ll
EXT
C3
4
  
— —
ee ff
IX2
D3
5
ff
IX1
E3
4
IX
F3
3
dd
DIR
3A
5
INH
4A
3
 
— —
INH
5A
3
IX1
6A
6
ff
IX
7A
5
ii
IMM
A8
2
dd
DIR
B8
3
hh ll
EXT
C8
4
 
— —
ee ff
IX2
D8
5
ff
IX1
E8
4
IX
F8
3
dd
DIR
3C
5
INH
4C
3
 
— —
INH
5C
3
IX1
6C
6
ff
IX
7C
5
Technical Data
63

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