MC68HC705J1A Motorola, MC68HC705J1A Datasheet - Page 64

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MC68HC705J1A

Manufacturer Part Number
MC68HC705J1A
Description
Manufacturer
Motorola
Datasheet

Specifications of MC68HC705J1A

Case
DIP-20L
Central Processor Unit (CPU)
Table 3-6. Instruction Set Summary (Sheet 4 of 6)
Source
Operation
Form
JMP opr
JMP opr
JMP opr,X
Unconditional Jump
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
Jump to Subroutine
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
Load Accumulator with Memory Byte
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
Load Index Register with Memory Byte
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
Logical Shift Left (Same as ASL)
LSL opr,X
LSL ,X
LSR opr
LSRA
LSRX
Logical Shift Right
LSR opr,X
LSR ,X
MUL
Unsigned Multiply
NEG opr
NEGA
NEGX
Negate Byte (Two’s Complement)
NEG opr,X
NEG ,X
NOP
No Operation
ORA #opr
ORA opr
ORA opr
Logical OR Accumulator with Memory
ORA opr,X
ORA opr,X
ORA ,X
Technical Data
64
Description
PC
Jump Address
PC
(PC) + n (n = 1, 2, or 3)
Push (PCL); SP
(SP) – 1
Push (PCH); SP
(SP) – 1
PC
Effective Address
A
(M)
X
(M)
C
0
b7
b0
0
C
b7
b0
X : A
(X)
(A)
M
–(M) = $00 – (M)
A
–(A) = $00 – (A)
X
–(X) = $00 – (X)
M
–(M) = $00 – (M)
M
–(M) = $00 – (M)
A
(A)
(M)
Central Processor Unit (CPU)
Effect
on CCR
H I N Z C
dd
DIR
BC
2
hh ll
EXT
CC
3
ee ff
— — — — —
IX2
DC
4
ff
IX1
EC
3
IX
FC
2
dd
DIR
BD
5
hh ll
EXT
CD
6
ee ff
— — — — —
IX2
DD
7
ff
IX1
ED
6
IX
FD
5
ii
IMM
A6
2
dd
DIR
B6
3
hh ll
EXT
C6
4
 
— —
ee ff
IX2
D6
5
ff
IX1
E6
4
IX
F6
3
ii
IMM
AE
2
dd
DIR
BE
3
hh ll
EXT
CE
4
 
— —
ee ff
IX2
DE
5
ff
IX1
EE
4
IX
FE
3
dd
DIR
38
5
INH
48
3
  
— —
INH
58
3
IX1
68
6
ff
IX
78
5
dd
DIR
34
5
INH
44
3
 
— — 0
INH
54
3
IX1
64
6
ff
IX
74
5
0 — — — 0
INH
42
11
dd
DIR
30
5
INH
40
3
  
— —
INH
50
3
IX1
60
6
ff
IX
70
5
— — — — —
INH
9D
2
ii
IMM
AA
2
dd
DIR
BA
3
hh ll
EXT
CA
4
 
— —
ee ff
IX2
DA
5
ff
IX1
EA
4
IX
FA
3
MC68HC705J1A — Rev. 4.0
MOTOROLA

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