MC68HC705J1A

Manufacturer Part NumberMC68HC705J1A
ManufacturerMotorola
MC68HC705J1A datasheet
 


Specifications of MC68HC705J1A

CaseDIP-20L  
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Bit Manipulation
Branch
DIR
DIR
REL
DIR
INH
MSB
0
1
2
3
4
LSB
5
5
3
5
0
BRSET0
BSET0
BRA
NEG
NEGA
3
DIR
2
DIR
2
REL
2
DIR
1
5
5
3
1
BRCLR0
BCLR0
BRN
3
DIR
2
DIR
2
REL
5
5
3
2
BRSET1
BSET1
BHI
MUL
3
DIR
2
DIR
2
REL
1
5
5
3
5
3
BRCLR1
BCLR1
BLS
COM
COMA
3
DIR
2
DIR
2
REL
2
DIR
1
5
5
3
5
4
BRSET2
BSET2
BCC
LSR
LSRA
3
DIR
2
DIR
2
REL
2
DIR
1
5
5
3
5
BRCLR2
BCLR2
BCS/BLO
3
DIR
2
DIR
2
REL
5
5
3
5
6
BRSET3
BSET3
BNE
ROR
RORA
3
DIR
2
DIR
2
REL
2
DIR
1
5
5
3
5
7
BRCLR3
BCLR3
BEQ
ASR
ASRA
3
DIR
2
DIR
2
REL
2
DIR
1
5
5
3
5
8
BRSET4
BSET4
BHCC
ASL/LSL
ASLA/LSLA
3
DIR
2
DIR
2
REL
2
DIR
1
5
5
3
5
9
BRCLR4
BCLR4
BHCS
ROL
ROLA
3
DIR
2
DIR
2
REL
2
DIR
1
5
5
3
5
A
BRSET5
BSET5
BPL
DEC
DECA
3
DIR
2
DIR
2
REL
2
DIR
1
5
5
3
B
BRCLR5
BCLR5
BMI
3
DIR
2
DIR
2
REL
5
5
3
5
C
BRSET6
BSET6
BMC
INC
INCA
3
DIR
2
DIR
2
REL
2
DIR
1
5
5
3
4
D
BRCLR6
BCLR6
BMS
TST
TSTA
3
DIR
2
DIR
2
REL
2
DIR
1
5
5
3
E
BRSET7
BSET7
BIL
3
DIR
2
DIR
2
REL
5
5
3
5
F
BRCLR7
BCLR7
BIH
CLR
CLRA
3
DIR
2
DIR
2
REL
2
DIR
1
INH = Inherent
REL = Relative
IMM = Immediate
IX = Indexed, No Offset
DIR = Direct
IX1 = Indexed, 8-Bit Offset
EXT = Extended
IX2 = Indexed, 16-Bit Offset
Table 3-7. Opcode Map
Read-Modify-Write
Control
INH
IX1
IX
INH
INH
5
6
7
8
9
3
3
6
5
9
NEGX
NEG
NEG
RTI
INH
1
INH
2
IX1
1
IX
1
INH
6
RTS
1
INH
11
INH
3
3
6
5
10
COMX
COM
COM
SWI
INH
1
INH
2
IX1
1
IX
1
INH
3
3
6
5
LSRX
LSR
LSR
INH
1
INH
2
IX1
1
IX
3
3
6
5
RORX
ROR
ROR
INH
1
INH
2
IX1
1
IX
3
3
6
5
ASRX
ASR
ASR
TAX
INH
1
INH
2
IX1
1
IX
1
INH
3
3
6
5
ASLX/LSLX
ASL/LSL
ASL/LSL
CLC
INH
1
INH
2
IX1
1
IX
1
INH
3
3
6
5
ROLX
ROL
ROL
SEC
INH
1
INH
2
IX1
1
IX
1
INH
3
3
6
5
DECX
DEC
DEC
CLI
INH
1
INH
2
IX1
1
IX
1
INH
SEI
1
INH
3
3
6
5
INCX
INC
INC
RSP
INH
1
INH
2
IX1
1
IX
1
INH
3
3
5
4
TSTX
TST
TST
NOP
INH
1
INH
2
IX1
1
IX
1
INH
2
STOP
1
INH
3
3
6
5
2
CLRX
CLR
CLR
WAIT
TXA
INH
1
INH
2
IX1
1
IX
1
INH
1
INH
LSB of Opcode in Hexadecimal
Register/Memory
IMM
DIR
EXT
IX2
IX1
A
B
C
D
E
2
3
4
5
4
SUB
SUB
SUB
SUB
SUB
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
2
3
4
5
4
CMP
CMP
CMP
CMP
CMP
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
2
3
4
5
4
SBC
SBC
SBC
SBC
SBC
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
2
3
4
5
4
CPX
CPX
CPX
CPX
CPX
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
2
3
4
5
4
AND
AND
AND
AND
AND
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
2
3
4
5
4
BIT
BIT
BIT
BIT
BIT
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
2
3
4
5
4
LDA
LDA
LDA
LDA
LDA
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
2
4
5
6
5
STA
STA
STA
STA
2
DIR
3
EXT
3
IX2
2
IX1
1
2
2
3
4
5
4
EOR
EOR
EOR
EOR
EOR
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
2
2
3
4
5
4
ADC
ADC
ADC
ADC
ADC
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
2
2
3
4
5
4
ORA
ORA
ORA
ORA
ORA
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
2
2
3
4
5
4
ADD
ADD
ADD
ADD
ADD
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
2
2
3
4
3
JMP
JMP
JMP
JMP
2
DIR
3
EXT
3
IX2
2
IX1
1
2
6
5
6
7
6
BSR
JSR
JSR
JSR
JSR
2
REL
2
DIR
3
EXT
3
IX2
2
IX1
1
2
3
4
5
4
LDX
LDX
LDX
LDX
LDX
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
2
4
5
6
5
STX
STX
STX
STX
2
DIR
3
EXT
3
IX2
2
IX1
1
MSB
0
MSB of Opcode in Hexadecimal
LSB
5
Number of Cycles
0
BRSET0
Opcode Mnemonic
3
DIR
Number of Bytes/Addressing Mode
IX
MSB
F
LSB
3
0
SUB
IX
3
1
CMP
IX
3
2
SBC
IX
3
3
CPX
IX
3
4
AND
IX
3
5
BIT
IX
3
6
LDA
IX
4
7
STA
IX
3
8
EOR
IX
3
9
ADC
IX
3
A
ORA
IX
3
B
ADD
IX
2
C
JMP
IX
5
D
JSR
IX
3
E
LDX
IX
4
F
STX
IX