MC68HC705J1A

Manufacturer Part NumberMC68HC705J1A
ManufacturerMotorola
MC68HC705J1A datasheet
 


Specifications of MC68HC705J1A

CaseDIP-20L  
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Page 72/162:

Resets and Interrupts

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Resets and Interrupts

4.3.2 External Reset
A logic 0 applied to the RESET pin for 1 1/2 t
reset. A Schmitt trigger senses the logic level at the RESET pin.
INTERNAL
INTERNAL
ADDRESS BUS
INTERNAL
DATA BUS
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
RESET pulse width
4.3.3 COP Watchdog Reset
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the
COP register at location $07F0.
4.3.4 Illegal Address Reset
An opcode fetch from an address not in random-access memory (RAM)
or erasable, programmable read-only memory (EPROM) generates a
reset.
Technical Data
72
CLOCK
$07FE
$07FE
$07FE
t
RL
RESET
Figure 4-3. External Reset Timing
Table 4-1. External Reset Timing
Characteristic

Resets and Interrupts

generates an external
cyc
$07FE
$07FF
NEW PC
NEW PC
NEW
NEW
OP
DUMMY
PCH
PCL
CODE
Symbol
Min
Max
Unit
t
t
1.5
RL
cyc
MC68HC705J1A — Rev. 4.0
MOTOROLA