MC68HC705J1A Motorola, MC68HC705J1A Datasheet - Page 73

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MC68HC705J1A

Manufacturer Part Number
MC68HC705J1A
Description
Manufacturer
Motorola
Datasheet

Specifications of MC68HC705J1A

Case
DIP-20L
4.4 Interrupts
These sources can generate interrupts:
An interrupt temporarily stops the program sequence to process a
particular event. An interrupt does not stop the operation of the
instruction being executed, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
CPU registers on the stack and loads the program counter with a
user-defined interrupt vector address.
4.4.1 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
4.4.2 External Interrupt
An interrupt signal on the IRQ/V
request. When the CPU completes its current instruction, it tests the IRQ
latch. If the IRQ latch is set, the CPU then tests the I bit in the condition
code register. If the I bit is clear, the CPU then begins the interrupt
sequence.
MC68HC705J1A — Rev. 4.0
MOTOROLA
Software interrupt (SWI) instruction
External interrupt pins:
– IRQ/V
PP
– PA0–PA3
Timer:
– Real-time interrupt flag (RTIF)
– Timer overflow flag (TOF)
PP
Resets and Interrupts
Resets and Interrupts
pin latches an external interrupt
Technical Data
Interrupts
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