MC68HC705J1A

Manufacturer Part NumberMC68HC705J1A
ManufacturerMotorola
MC68HC705J1A datasheet
 


Specifications of MC68HC705J1A

CaseDIP-20L  
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Page 74/162

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Resets and Interrupts
The CPU clears the IRQ latch during interrupt processing, so that
another interrupt signal on the IRQ/V
request during the interrupt service routine. As soon as the I bit is cleared
during the return from interrupt, the CPU can recognize the new interrupt
request.
IRQ
PA3
PA2
PA1
PA0
Setting the I bit in the condition code register disables external interrupts.
The port A external interrupt bit (PIRQ) in the mask option register
enables pins PA0–PA3 to function as external interrupt pins.
The external interrupt sensitivity bit (LEVEL) in the mask option register
controls interrupt triggering sensitivity of external interrupt pins. The
IRQ/V
low-level triggered. Port A external interrupt pins can be positive-edge
triggered only or both positive-edge and high-level triggered. The
level-sensitive triggering option allows multiple external interrupt
sources to be wire-ORed to an external interrupt pin. An external
interrupt request, shown in
is holding an external interrupt pin low.
Technical Data
74
Figure 4-4
shows the IRQ/V
LEVEL-SENSITIVE TRIGGER
(MOR LEVEL BIT)
V
DD
D
LATCH
CK
PIRQ
(MOR)
RESET
IRQ VECTOR FETCH
IRQR
Figure 4-4. External Interrupt Logic
pin can be negative-edge triggered only or negative-edge and
PP
Figure
4-5, is latched as long as any source
Resets and Interrupts
pin can latch another interrupt
PP
pin interrupt logic.
PP
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQF
EXTERNAL
IRQ
Q
INTERRUPT
REQUEST
IRQE
CLR
MC68HC705J1A — Rev. 4.0
MOTOROLA