MC68HC705J1A Motorola, MC68HC705J1A Datasheet - Page 76

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MC68HC705J1A

Manufacturer Part Number
MC68HC705J1A
Description
Manufacturer
Motorola
Datasheet

Specifications of MC68HC705J1A

Case
DIP-20L
Resets and Interrupts
4.4.3 Timer Interrupts
The timer can generate these interrupt requests:
Setting the I bit in the condition code register disables timer interrupts.
4.4.3.1 Real-Time Interrupt
A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes
set while the real-time interrupt enable bit, RTIE, is also set. RTIF and
RTIE are in the timer status and control register.
4.4.3.2 Timer Overflow Interrupt
A timer overflow interrupt request occurs if the timer overflow flag, TOF,
becomes set while the timer overflow interrupt enable bit, TOIE, is also
set. TOF and TOIE are in the timer status and control register.
4.4.4 Interrupt Processing
The CPU takes these actions to begin servicing an interrupt:
The return-from-interrupt (RTI) instruction causes the CPU to recover
the CPU registers from the stack as shown in
Technical Data
76
Real time
Timer overflow
Stores the CPU registers on the stack in the order shown in
Figure 4-6
Sets the I bit in the condition code register to prevent further
interrupts
Loads the program counter with the contents of the appropriate
interrupt vector locations:
– $07FC and $07FD (software interrupt vector)
– $07FA and $07FB (external interrupt vector)
– $07F8 and $07F9 (timer interrupt vector)
Resets and Interrupts
Figure
4-6.
MC68HC705J1A — Rev. 4.0
MOTOROLA

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