MC68HC705J1A

Manufacturer Part NumberMC68HC705J1A
ManufacturerMotorola
MC68HC705J1A datasheet
 

Specifications of MC68HC705J1A

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Page 80/162:

Low-Power Modes

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Low-Power Modes

5.3 Exiting Stop and Wait Modes
The events described in this subsection bring the MCU out of stop mode
and load the program counter with the reset vector or with an interrupt
vector.
Exiting stop mode:
Exiting wait mode:
Technical Data
80
Enabling halt mode prevents the computer operating properly
(COP) watchdog from being inadvertently turned off by a STOP
instruction.
Data-retention mode — In data-retention mode, the MCU retains
RAM contents and CPU register contents at V
as 2.0 Vdc. The data-retention feature allows the MCU to remain
in a low power-consumption state during which it retains data, but
the CPU cannot execute instructions.
External reset — A logic 0 on the RESET pin resets the MCU,
starts the CPU clock, and loads the program counter with the
contents of locations $07FE and $07FF.
External interrupt — A high-to-low transition on the IRQ/V
a low-to-high transition on an enabled port A external interrupt pin
starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
External reset — A logic 0 on the RESET pin resets the MCU,
starts the CPU clock, and loads the program counter with the
contents of locations $07FE and $07FF.
External interrupt — A high-to-low transition on the IRQ/V
a low-to-high transition on an enabled port A external interrupt pin
starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.

Low-Power Modes

voltages as low
DD
pin or
PP
pin or
PP
MC68HC705J1A — Rev. 4.0
MOTOROLA