MC68HC705J1A

Manufacturer Part NumberMC68HC705J1A
ManufacturerMotorola
MC68HC705J1A datasheet
 


Specifications of MC68HC705J1A

CaseDIP-20L  
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Page 90/162

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Parallel Input/Output (I/O) Ports
6.3.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is
an input or an output.
Address:
Read:
Write:
Reset:
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 6-4
Technical Data
90
$0004
Bit 7
6
5
4
DDRA7
DDRA6
DDRA5
DDRA4
0
0
0
0
Figure 6-3. Data Direction Register A (DDRA)
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
shows the I/O logic of port A.
READ DDRA
WRITE DDRA
DDRAx
WRITE PORTA
PAx
READ PORTA
WRITE PDRA
PDRAx
RESET
Figure 6-4. Port A I/O Circuitry
Parallel Input/Output (I/O) Ports
3
2
1
Bit 0
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
10-mA SINK CAPABILITY
(PINS PA4–PA7 ONLY)
PAx
(PA0–PA3 TO
IRQ MODULE)
100- A
PULLDOWN
SWPDI
MC68HC705J1A — Rev. 4.0
MOTOROLA