MC68HC705J1A

Manufacturer Part NumberMC68HC705J1A
ManufacturerMotorola
MC68HC705J1A datasheet
 

Specifications of MC68HC705J1A

CaseDIP-20L  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Page 91
92
Page 92
93
Page 93
94
Page 94
95
Page 95
96
Page 96
97
Page 97
98
Page 98
99
Page 99
100
Page 100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
Page 92/162:

Port B

Download datasheet (2Mb)Embed
PrevNext
Parallel Input/Output (I/O) Ports
6.3.4 Port A LED Drive Capability
The outputs for the upper four bits of port A (PA4–PA7) can drive
light-emitting diodes (LEDs). PA4–PA7 can sink approximately 10 mA of
current to V
6.3.5 Port A I/O Pin Interrupts
If the PIRQ bit in the mask option register is programmed to logic 1,
PA0–PA3 pins function as external interrupt pins. See
External Interrupt Module
6.4 Port B
Port B is a 6-bit bidirectional port.
6.4.1 Port B Data Register
The port B data register (PORTB) contains a latch for each port B pin.
Address:
Read:
Write:
Reset:
PB[5:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
Technical Data
92
.
SS
(IRQ).
$0001
Bit 7
6
5
4
0
0
PB5
PB4
Unaffected by reset
= Unimplemented
Figure 6-6. Port B Data Register (PORTB)
Parallel Input/Output (I/O) Ports
Section 8.
3
2
1
Bit 0
PB3
PB2
PB1
PB0
MC68HC705J1A — Rev. 4.0
MOTOROLA