MC68HC705J1A

Manufacturer Part NumberMC68HC705J1A
ManufacturerMotorola
MC68HC705J1A datasheet
 

Specifications of MC68HC705J1A

CaseDIP-20L  
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Page 94/162

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Parallel Input/Output (I/O) Ports
Writing a logic 1 to a DDRB bit enables the output buffer for the
corresponding port B pin; a logic 0 disables the output buffer.
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data
latch. When bit DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
of the port B pins.
Data Direction Bit
1. Writing affects the data register, but does not affect input.
6.4.3 Pulldown Register B
Pulldown register B (PDRB) inhibits the pulldown devices on port B pins
programmed as inputs.
NOTE:
If the SWPDI bit in the mask option register is programmed to logic 1,
reset initializes all port B pins as inputs with disabled pulldown devices.
Address:
Read:
Write:
Reset:
PDIB[7:0] — Pulldown Inhibit B Bits
PDIB[7:0] disable the port B pulldown devices. Reset clears
PDIB[7:0].
Technical Data
94
Table 6-2. Port B Pin Operation
I/O Pin Mode
0
Input, high-impedance
1
Output
$0011
Bit 7
6
5
4
PDIB5
PDIB4
0
0
= Unimplemented
Figure 6-9. Pulldown Register B (PDRB)
1 = Corresponding port B pulldown device disabled
0 = Corresponding port B pulldown device not disabled
Parallel Input/Output (I/O) Ports
Table 6-2
summarizes the operation
Accesses to Data Bit
Read
Write
Pin
Latch
Latch
Latch
3
2
1
PDIB3
PDIB2
PDIB1
0
0
0
MC68HC705J1A — Rev. 4.0
MOTOROLA
(1)
Bit 0
PDIB0
0