MC68HC705J1A

Manufacturer Part NumberMC68HC705J1A
ManufacturerMotorola
MC68HC705J1A datasheet
 


Specifications of MC68HC705J1A

CaseDIP-20L  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Page 91
92
Page 92
93
Page 93
94
Page 94
95
Page 95
96
Page 96
97
Page 97
98
Page 98
99
Page 99
100
Page 100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
Page 99/162:

COP Register

Download datasheet (2Mb)Embed
PrevNext
Clearing the COP bit disables the COP watchdog timer regardless of the
IRQ/V
If the main program executes within the COP timeout period, the clearing
routine should be executed only once. If the main program takes longer
than the COP timeout period, the clearing routine must be executed
more than once.
NOTE:
Place the clearing routine in the main program and not in an interrupt
routine. Clearing the COP watchdog in an interrupt routine might prevent
COP watchdog timeouts even though the main program is not operating
properly.
7.4 Interrupts
The COP watchdog does not generate interrupts.
7.5 COP Register
The COP register (COPR) is a write-only register that returns the
contents of EPROM location $07F0 when read.
Address:
Read:
Write:
Reset:
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. Reading address $07F0
returns undefined results.
MC68HC705J1A — Rev. 4.0
MOTOROLA
pin voltage.
PP
$07F0
Bit 7
6
5
= Unimplemented
Figure 7-1. COP Register (COPR)
Computer Operating Properly (COP) Module
Computer Operating Properly (COP) Module
4
3
2
1
Technical Data
Interrupts
Bit 0
COPC
0
99