MC68HC705J1A Cop Register - Motorola

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MC68HC705J1A

Manufacturer Part Number
MC68HC705J1A
Description
Manufacturer
Motorola
Datasheet

Specifications of MC68HC705J1A

Case
DIP-20L
Clearing the COP bit disables the COP watchdog timer regardless of the
IRQ/V
If the main program executes within the COP timeout period, the clearing
routine should be executed only once. If the main program takes longer
than the COP timeout period, the clearing routine must be executed
more than once.
NOTE:
Place the clearing routine in the main program and not in an interrupt
routine. Clearing the COP watchdog in an interrupt routine might prevent
COP watchdog timeouts even though the main program is not operating
properly.
7.4 Interrupts
The COP watchdog does not generate interrupts.
7.5 COP Register
The COP register (COPR) is a write-only register that returns the
contents of EPROM location $07F0 when read.
Address:
Read:
Write:
Reset:
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. Reading address $07F0
returns undefined results.
MC68HC705J1A — Rev. 4.0
MOTOROLA
pin voltage.
PP
$07F0
Bit 7
6
5
= Unimplemented
Figure 7-1. COP Register (COPR)
Computer Operating Properly (COP) Module
Computer Operating Properly (COP) Module
4
3
2
1
Technical Data
Interrupts
Bit 0
COPC
0
99

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