MC68HC705X32 Freescale Semiconductor, Inc, MC68HC705X32 Datasheet

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MC68HC705X32

Manufacturer Part Number
MC68HC705X32
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Freescale Semiconductor, Inc.
MC68HC05X16/D
Rev. 1
HC05
MC68HC05X16
MC68HC05X32
MC68HC705X32
TECHNICAL
DATA

Related parts for MC68HC705X32

MC68HC705X32 Summary of contents

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... Freescale Semiconductor, Inc. HC05 MC68HC05X16 MC68HC05X32 MC68HC705X32 TECHNICAL DATA MC68HC05X16/D Rev. 1 ...

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For More Information On This Product, Go to: www.freescale.com ...

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... Freescale Semiconductor, Inc. MODES OF OPERATION AND PIN DESCRIPTIONS MOTOROLA CAN MODULE (MCAN) SERIAL COMMUNICATIONS INTERFACE PULSE LENGTH D/A CONVERTERS ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS For More Information On This Product, Go to: www.freescale.com INTRODUCTION MEMORY AND REGISTERS INPUT/OUTPUT PORTS ...

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... Freescale Semiconductor, Inc. 1 INTRODUCTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS 3 MEMORY AND REGISTERS 4 INPUT/OUTPUT PORTS 5 MOTOROLA CAN MODULE (MCAN) 6 PROGRAMMABLE TIMER 7 SERIAL COMMUNICATIONS INTERFACE 8 PULSE LENGTH D/A CONVERTERS 9 ANALOG TO DIGITAL CONVERTER 10 RESETS AND INTERRUPTS 11 CPU CORE AND INSTRUCTION SET 12 ELECTRICAL SPECIFICATIONS 13 MECHANICAL DATA ...

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... Freescale Semiconductor, Inc. MC68HC05X16 MC68HC05X32 MC68HC705X32 High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. ...

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... Freescale Semiconductor, Inc. Conventions Where abbreviations are used in the text, an explanation can be found in the glossary, at the back of this manual. Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET. Unless otherwise stated, a shaded cell in a register diagram indicates that the bit is either unused or reserved ...

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... Freescale Semiconductor, Inc. CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05X16/D) Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you have just received. Having used the document, please complete this card (or a photocopy of it, if you prefer). 1. How would you rate the quality of the document? Check one box in each category. ...

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... Freescale Semiconductor, Inc. 8. How could we improve this document? 9. How would you rate Motorola’s documentation? – In general – Against other semiconductor suppliers 10. Which semiconductor manufacturer provides the best technical documentation? 11. Which company (in any field) provides the best technical documentation? 12. How many years have you worked with microprocessors? Less than 1 year 1– ...

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... Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Number 1.1 Features ................................................................................................................ 1-2 1.2 Mask options for the MC68HC05X16 .................................................................... 1-3 MODES OF OPERATION AND 2.1 Modes of operation................................................................................................ 2-1 2.1.1 Single-chip mode ............................................................................................. 2-1 2.1.2 Bootstrap mode ............................................................................................... 2-2 2.1.2.1 Serial RAM loader ...................................................................................... 2-3 2.1.2.2 Jump to RAM + 1 ....................................................................................... 2-3 2.1.2.3 ‘ ...

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... Freescale Semiconductor, Inc. Paragraph Number 2.3.12 OSC1, OSC2 ................................................................................................... 2-13 2.3.12.1 Crystal........................................................................................................ 2-13 2.3.12.2 Ceramic resonator ..................................................................................... 2-13 2.3.12.3 External clock............................................................................................. 2-13 2.3.12.4 Oscillator division ....................................................................................... 2-15 2.3.13 PLMA ............................................................................................................... 2-15 2.3.14 PLMB ............................................................................................................... 2-15 2.3.15 VPP1 ............................................................................................................... 2-16 2.3.16 VRH ................................................................................................................. 2-16 2.3.17 VRL.................................................................................................................. 2-16 2.3.18 PA0 – PA7/PB0 – PB7/PC0 – PC7 .................................................................. 2-16 2 ...

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... Freescale Semiconductor, Inc. Paragraph Number 4.5.1 Port data registers A and B (PORTA and PORTB) .......................................... 4-4 4.5.2 Port data register C (PORTC).......................................................................... 4-5 4.5.3 Port data register D (PORTD).......................................................................... 4-5 4.5.4 A/D status/control register ............................................................................... 4-5 4.5.5 Data direction registers (DDRA, DDRB and DDRC)........................................ 4-6 4.6 Other port considerations ...

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... Freescale Semiconductor, Inc. Paragraph Number 6.4 Output compare..................................................................................................... 6-9 6.4.1 Output compare register 1 (OCR1) ................................................................. 6-9 6.4.2 Output compare register 2 (OCR2) ................................................................. 6-10 6.4.3 Software force compare................................................................................... 6-11 6.5 Pulse length modulation (PLM) ............................................................................. 6-11 6.5.1 Pulse length modulation registers A and B (PLMA/PLMB).............................. 6-11 6.6 Timer during STOP mode ...

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... Freescale Semiconductor, Inc. Paragraph Number ANALOG TO DIGITAL CONVERTER 9.1 A/D converter operation......................................................................................... 9-1 9.2 A/D registers.......................................................................................................... 9-3 9.2.1 Port D data register (PORTD).......................................................................... 9-3 9.2.2 A/D result data register (ADDATA) ................................................................... 9-3 9.2.3 A/D status/control register (ADSTAT)............................................................... 9-4 9.3 A/D converter during STOP mode......................................................................... 9-5 9 ...

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... Freescale Semiconductor, Inc. Paragraph Number 11.2.1 Register/memory Instructions........................................................................ 11-4 11.2.2 Branch instructions ........................................................................................ 11-4 11.2.3 Bit manipulation instructions.......................................................................... 11-4 11.2.4 Read/modify/write instructions....................................................................... 11-4 11.2.5 Control instructions........................................................................................ 11-4 11.2.6 Tables ............................................................................................................ 11-4 11.3 Addressing modes............................................................................................... 11-11 11.3.1 Inherent ......................................................................................................... 11-11 11.3.2 Immediate ...................................................................................................... 11-11 11.3.3 Direct ............................................................................................................. 11-11 11 ...

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... EPROM electrical characteristics ....................................................................B-26 B.9.4 Control timing...................................................................................................B-27 B.9.5 A/D converter characteristics...........................................................................B-28 B.9.6 MCAN bus interface DC electrical characteristics ...........................................B-29 B.9.7 MCAN bus interface control timing characteristics ..........................................B-29 MC68HC05X16 For More Information On This Product, Go to: www.freescale.com TITLE A MC68HC05X32 B MC68HC705X32 TABLE OF CONTENTS Page Number vii ...

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... Freescale Semiconductor, Inc. Paragraph Number C.1 DC electrical characteristics ..................................................................................C-1 C.2 Control Timing .......................................................................................................C-2 For More Information On This Product, TITLE C MC68HC05X32 HIGH SPEED OPERATION TABLE OF CONTENTS Go to: www.freescale.com Page Number MC68HC05X16 Rev. 1 ...

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... Freescale Semiconductor, Inc. LIST OF FIGURES Figure Number 1-1 MC68HC05X16 block diagram ............................................................................... 1-4 2-1 Bootstrap mode function selection flow chart......................................................... 2-2 2-2 MC68HC05X16 ‘jump to any address’ schematic diagram..................................... 2-4 2-3 MC68HC05X16 ‘load program in RAM and execute’ schematic diagram............... 2-5 2-4 STOP and WAIT fl ...

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... A-2 Memory map of the MC68HC05X32 ...................................................................... A-3 A-3 Timer relationship................................................................................................... A-11 B-1 MC68HC705X32 block diagram............................................................................. B-3 B-2 Memory map of the MC68HC705X32 .................................................................... B-5 B-3 Modes of operation flow chart ................................................................................ B-15 B-4 Timing diagram with handshake............................................................................. B-18 B-5 Parallel EPROM loader timing diagram.................................................................. B-18 B-6 EPROM parallel bootstrap schematic diagram ...

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... Freescale Semiconductor, Inc. LIST OF TABLES Table Number 1-1 Data sheet appendices........................................................................................... 1-1 2-1 Mode of operation selection ................................................................................... 2-1 3-1 EEPROM control bits description ........................................................................... 3-6 3-2 MC68HC05X16 register outline.............................................................................. 3-9 3-3 MCAN register outline ............................................................................................ 3-10 3-4 IRQ and WOI sensitivity ......................................................................................... 3-11 4-1 I/O pin states .......................................................................................................... 4-2 5-1 Synchronization jump width ...

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... Freescale Semiconductor, Inc. Table Number 11-7 Instruction set........................................................................................................11-8 11-8 M68HC05 opcode map .........................................................................................11-10 12-1 Absolute maximum ratings ....................................................................................12-1 12-2 DC electrical characteristics..................................................................................12-2 12-3 A/D characteristics ................................................................................................12-4 12-4 Control timing ........................................................................................................12-5 12-5 MCAN bus interface DC electrical characteristics.................................................12-6 12-6 MCAN bus interface control timing characteristics................................................12-6 14-1 MC order numbers ...

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... This data sheet is structured such that devices similar to the MC68HC05X16 are described in a set of appendices (see Table 1-1). Table 1-1 Data sheet appendices Device Appendix MC68HC05X32 MC68HC705X32 MC68HC05X32 Note: Appendix C contains only electrical characteristics exclusive to the high speed operation of the MC68HC05X32. For all other information concerning this device, refer to Appendix A ...

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... Freescale Semiconductor, Inc. 1 1.1 Features Hardware features • Fully static design featuring the industry standard M68HC05 family CPU core • On chip crystal oscillator with divide-by -2, - -10 software selectable divide-by -32, -64, -128 or -160 option (SLOW mode) • 352 bytes of RAM • 15102 bytes of user ROM plus 16 bytes of user vectors • ...

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... Freescale Semiconductor, Inc. 1.2 Mask options for the MC68HC05X16 The MC68HC05X16 has six mask options that are programmed during manufacture and must be specified on the order form. • Oscillator division ratio selection (divide-by-2, - -10) • Oscillator start-up delay following power-on or STOP (t • ...

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... Freescale Semiconductor, Inc. 1 VPP1 RESET IRQ OSC2 OSC1 VDD1 VSS1 VDDH TX0 interface TX1 RX0 RX1 NWOI MDS VDD VSS PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL 256 bytes EEPROM 15118 bytes user ROM Charge pump (including 16 bytes ...

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... Freescale Semiconductor, Inc. MODES OF OPERATION AND PIN DESCRIPTIONS 2.1 Modes of operation The MC68HC05X16 MCU has two modes of operation, single-chip mode and bootstrap mode. In the MC68HC05X16 the single-chip mode is the normal user operating frequency the conditions required to enter each mode on the rising edge of RESET . ...

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... Freescale Semiconductor, Inc. 2.1.2 Bootstrap mode 2 To place the part in bootstrap mode, the following conditions must be met during transition of the RESET pin from low to high: 1) IRQ pin at 2xV 2) TCAP1 pin TCAP2 pin at V PD4 and PD3 are connected according to the values given in function from the following three functions: • ...

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... Freescale Semiconductor, Inc. Note: Oscillator divide-by-two is forced in bootstrap mode; all other mask options are selected by the customer (see Section 2.1.2.1 Serial RAM loader In the ‘load program in RAM and execute’ routine, user programs are loaded into MCU RAM via the SCI port and then executed. Data is loaded sequentially, starting at RAM location $0050, until the last byte is loaded. The fi ...

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... Freescale Semiconductor, Inc. 2 RESET 0. optional (see note Note: These eight resistors are optional; direct connection is possible if pins PA0-PA7, PB0-PB7 and PC0-PC7 are kept in input mode during application. Figure 2-2 MC68HC05X16 ‘jump to any address’ schematic diagram MODES OF OPERATION AND PIN DESCRIPTIONS ...

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... Freescale Semiconductor, Inc RESET RESET 0.01 mF 9600 Bd RS232 level translator RDI suggested: TDO RS232 MC145406 or MAX232 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 Connect as required PB3 for the application PB2 PB1 PB0 PC7 PC6 PC5 PC4 ...

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... Freescale Semiconductor, Inc. 2.2 Low power modes 2 The STOP and WAIT instructions have different effects on the programmable timer, the serial communications interface, the watchdog system, the EEPROM and the A/D converter. These different effects are described in the following sections. 2.2.1 STOP mode The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the internal oscillator is turned off (providing the MCAN is ‘ ...

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... Freescale Semiconductor, Inc. 2.2.2 WAIT mode The WAIT instruction places the MCU in a low power consumption mode, but WAIT mode consumes more power than STOP mode. All CPU action is suspended and the watchdog is disabled, but the timer, A/D and SCI and MCAN systems remain active and operate as normal (see fl ...

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... Freescale Semiconductor, Inc. The following list summarizes the effect of WAIT mode on the modules of the MC68HC05X16. 2 – The watchdog timer functions according to the mask option selected; see Section 10.1.4.2 – The EEPROM is not affected; see – The SCI is not affected; see – The timer is not affected; see – ...

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... Freescale Semiconductor, Inc. STOP YES Watchdog active? NO Stop oscillator and all clocks. Clear I bit. NO Reset ? CIRQ, NO YES wired-OR, external interrupt? YES Turn on oscillator. Wait for time delay to stabilise Generate watchdog interrupt (1) Fetch reset vector or (2) Service interrupt: a. stack b. set I-bit c. vector to interrupt routine Figure 2-4 STOP and WAIT fl ...

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... Freescale Semiconductor, Inc. OSC1 2 pin Oscillator SM–bit (bit 1, $000C) Note: 2.2.3.1 Miscellaneous register Miscellaneous SM — Slow mode 1 (set) – The system runs at a bus speed 16 times lower than normal (f /64, /128 or /160). SLOW mode affects all sections of the device (including SCI, A/D and timer) except for the MCAN module. ...

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... Freescale Semiconductor, Inc. 2.3 Pin descriptions 2.3.1 VDD and VSS Power is supplied to the microcontroller using these two pins. VDD is the positive supply and VSS is ground the nature of CMOS designs that very fast signal transitions occur on the MCU pins. These short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care must be taken to provide good power supply bypassing at the MCU ...

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... Freescale Semiconductor, Inc. 2.3.4 MDS 2 A pull-down device is activated on this pin each time the RESET pin is pulled low. Even after the RESET pin is pulled high, the pull-down on the MDS pin will remain active until the pin is pulled high. In single-chip mode MDS can be connected to VSS or left floating. When MDS is tied the end of reset used to select any mode of operation other than single-chip mode ...

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... Freescale Semiconductor, Inc. 2.3.11 SCLK The SCLK pin is the clock output pin of the SCI transmitter. 2.3.12 OSC1, OSC2 These pins provide control input for an on-chip oscillator circuit. A crystal, ceramic resonator or external clock signal connected to these pins supplies the oscillator clock. The oscillator frequency ...

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... Freescale Semiconductor, Inc. 2 OSC1 COSC1 (a) Crystal/ceramic resonator oscillator connections R (max – – 30 OSC1 C 15 – – 25 OSC2 Q 30 000 MODES OF OPERATION AND PIN DESCRIPTIONS OSC1 MCU OSC2 COSC2 (c) External clock source connections Crystal 2MHz 4MHz Unit 400 ƒ 000 — (d) Typical crystal and ceramic resonator parameters ...

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... Freescale Semiconductor, Inc. 2.3.12.4 Oscillator division The external oscillator can run up to 22MHz. For this reason an additional clock predivider is provided; its division ratio is selected via a mask option (see two, four, eight or ten times slower than the external clock, provided that SLOW mode has not been entered ...

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... Freescale Semiconductor, Inc. 2.3.15 VPP1 2 The VPP1 pin is the output of the charge pump for the EEPROM1 array. 2.3.16 VRH The VRH pin is the positive reference voltage for the A/D converter. 2.3.17 VRL The VRL pin is the negative reference voltage for the A/D converter. ...

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... Freescale Semiconductor, Inc. 2.3.21 VDD1 This pin is the power input for the input comparator of the MCAN module. 2.3.22 VSS1 This pin is the ground connection for the input comparator of the MCAN bus. 2.3.23 VDDH This pin provides the high voltage reference output for the MCAN bus. The output voltage is equal to VDD 2 ...

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... Freescale Semiconductor, Inc. 2 THIS PAGE LEFT BLANK INTENTIONALLY MODES OF OPERATION AND PIN DESCRIPTIONS For More Information On This Product, Go to: www.freescale.com MC68HC05X16 Rev. 1 ...

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... Freescale Semiconductor, Inc. MEMORY AND REGISTERS The MC68HC05X16 MCU is capable of addressing 16384 bytes of memory and registers with its program counter. The memory map includes 15118 bytes of user ROM (including user vectors), 576 bytes of bootstrap ROM, 352 bytes of RAM and 256 bytes of EEPROM. ...

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... Freescale Semiconductor, Inc. MC68HC05X16 $0000 3 I/O (32 bytes) $0020 MCAN registers $003E $0050 RAM I (176 bytes) $00C0 Stack $0100 OPTR (1 byte) $0101 Non protected (31 bytes) $0120 EEPROM (256 bytes) Protected (224 bytes) $0200 Bootstrap ROM I (80 bytes) $0250 RAM II 176 bytes $0300 ...

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... Freescale Semiconductor, Inc. MCAN register blocks $0020 MCAN control registers 10 bytes $0029 $002A MCAN transmit buffer 10 bytes $0033 $0034 MCAN receive buffer 10 bytes $003D Figure 3-2 MCAN module memory map 3.4 Bootstrap ROM There are two areas of bootstrap ROM (ROMI and ROMII) located from $0200 to $024F (80 bytes) and $3DFE to $3FEF (498 bytes) respectively ...

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... Freescale Semiconductor, Inc. 3.5 EEPROM The user EEPROM consists of 256 bytes of memory located from address $0100 to $01FF. 255 bytes are general purpose and 1 byte is used by the option register. The non-volatile EEPROM is byte erasable internal charge pump provides the EEPROM voltage (V a high voltage for erase and programming functions. The charge pump is a capacitor/diode ladder network which will give a very high impedance output of around 20-30 M ...

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... Freescale Semiconductor, Inc. CAF — MCAN asleep flag This flag is set by the MCU when the MCAN module enters SLEEP mode. This is the only indication that the MCAN is asleep (see 1 (set) – The MCAN module is in SLEEP mode. 0 (clear) – The MCAN module is not in SLEEP mode. ...

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... Freescale Semiconductor, Inc. E1ERA 3.5.2 EEPROM read operation To be able to read from EEPROM, the E1LAT bit has logic zero, as shown in While this bit is at logic zero, the E1PGM bit and the E1ERA bit are permanently reset to zero and the 256 bytes of EEPROM may be read were a normal ROM area. The internal charge pump generator is automatically switched off since the E1PGM bit is reset ...

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... Freescale Semiconductor, Inc second word erased important that the E1LAT bit be reset before restarting the erasing sequence, otherwise any write to a new address will have no effect. This condition provides a higher degree of security for the stored data. User programs must be running from the RAM or ROM as the EEPROM will have its address and data buses latched ...

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... Freescale Semiconductor, Inc. EE1P – EEPROM protect bit In order to achieve a higher degree of protection, the EEPROM is effectively split into two parts, both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to $011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit of the options register ...

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... Freescale Semiconductor, Inc. Table 3-2 MC68HC05X16 register outline Register name Address bit 7 Port A data (PORTA) $0000 Port B data (PORTB) $0001 Port C data (PORTC) $0002 Port D data (PORTD) $0003 Port A data direction (DDRA) $0004 Port B data direction (DDRB) $0005 Port C data direction (DDRC) ...

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... Freescale Semiconductor, Inc. Register name Control (CCNTRL) 3 Command (CCOM) Status (CSTAT) Interrupt (CINT) (1) Acceptance code (CACC) (1) Acceptance mask (CACM) (1) Bus timing 0 (CBT0) (1) Bus timing 1 (CBT1) (1) Output control (COCNTRL) (reserved) Transmit buffer identifier (TBI) RTR-bit, data length code (TRTDL) Transmit data segment 1 (TDS1) ...

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... Freescale Semiconductor, Inc. 3.8 Miscellaneous register Address Miscellaneous $000C POR (1) The POR bit is set each time there is a power-on reset. (2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled. POR — Power-on reset bit (see This bit is set each time the device is powered on ...

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... Freescale Semiconductor, Inc. SFB — Slow or fast mode selection for PLMB (see 1 (set) – Slow mode PLMB (4096 x timer clock period). 0 (clear) – Fast mode PLMB (256 x timer clock period). 3 Note: The highest speed of the PLM system corresponds to the frequency of the TOF bit being set, multiplied by 256 ...

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... Freescale Semiconductor, Inc. INPUT/OUTPUT PORTS In single-chip mode, the MC68HC05X16 has a total of 24 I/O lines, arranged as three 8-bit ports (A, B and C), and eight input-only lines, arranged as one 8-bit port (D). Each I/O line is individually programmable as either input or output, under the software control of the data direction registers. ...

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... Freescale Semiconductor, Inc. Data direction register bit Latched data register bit 4 Table 4-1 shows the effect of reading from or writing to an I/O pin in various circumstances. Note that the read/write signal shown is internal and not available to the user. R/W DDRn 4.2 Ports A and B These ports are standard M68HC05 bidirectional I/O ports, each comprising a data register and a data direction register ...

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... Freescale Semiconductor, Inc. A mask option is provided to enable resistive pull downs on all port B pins that are programmed as inputs. 4.3 Port C In addition to the standard port functions described for ports A and B, port C pin 2 can be configured, using the ECLK bit of the EEPROM/ECLK control register, to output the CPU clock. If this is selected the corresponding DDR bit is automatically set and bit 2 of port C will always read the output data latch ...

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... Freescale Semiconductor, Inc. 4.4 Port D This 8-bit input-only port shares its pins with the A/D converter subsystem. When the A/D converter is enabled, pins PD0-PD7 read the eight analog inputs to the A/D converter. Port D can be read at any time, however read during an A/D conversion sequence noise, may be injected on the analog inputs, resulting in reduced accuracy of the A/D ...

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... Freescale Semiconductor, Inc. 4.5.2 Port data register C (PORTC) Address Port C data (PORTC) $0002 Each bit can be configured as input or output via the corresponding data direction bit in the port data direction register (DDRx). In addition, bit 2 of port C is used to output the CPU clock if the ECLK bit in the EEPROM ...

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... Freescale Semiconductor, Inc. 4.5.5 Data direction registers (DDRA, DDRB and DDRC) Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) 4 Writing a ‘1’ to any bit configures the corresponding port pin as an output; conversely, writing any bit to ‘0’ configures the corresponding port pin as an input. ...

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... Freescale Semiconductor, Inc. Read buffer output (a) Data direction register bit DDRn DDRn ( VDD Px0 MC68HC05X16 For More Information On This Product, Go to: www.freescale.com Normal operation – tri state 0 tri state 1 tri state 0 low 1 — ‘Open-drain’ 0 high 1 high ‘Open-drain’ output (c) DDRx, bit ...

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... Freescale Semiconductor, Inc. 4 THIS PAGE LEFT BLANK INTENTIONALLY INPUT/OUTPUT PORTS For More Information On This Product, Go to: www.freescale.com MC68HC05X16 Rev. 1 ...

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... Freescale Semiconductor, Inc. MOTOROLA CAN MODULE (MCAN) The MCAN includes all hardware modules necessary to implement the CAN transfer layer, which represents the kernel of the CAN bus protocol as defined by BOSCH GmbH, the originators of the CAN specification. For full details of the CAN protocol please refer to the published specifications. ...

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... Freescale Semiconductor, Inc. Acknowledge 5 frame Del Ack Del CRC DLC0 DLC3 RB0 bits Reserved RB1 RTR ID0 ID10 of Start Figure 5-2 MCAN frame formats MOTOROLA CAN MODULE (MCAN) For More Information On This Product, Go to: www.freescale.com Del Ack Acknowledge Del CRC DLC0 ...

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... Freescale Semiconductor, Inc. Figure 5-2 MCAN frame formats (Continued) MC68HC05X16 MOTOROLA CAN MODULE (MCAN) For More Information On This Product, Go to: www.freescale.com frame of Start 5 5-3 ...

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... Freescale Semiconductor, Inc. 5.1 TBF – Transmit buffer The transmit buffer is an interface between the CPU and the bit stream processor (BSP) and is able to store a complete message. The buffer is written by the CPU and read by the BSP. The CPU may access this buffer whenever transmit buffer access is set to released. On requesting a transmission (by setting transmission request in the MCAN command register to present) transmit buffer access is set to locked, giving the BSP exclusive access to this buffer ...

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... Freescale Semiconductor, Inc similar manner, the CPU module is notified that a message has been received only if it was error free. If any error occurs, the MCAN signals the error within the CAN protocol without CPU intervention. The MCAN within the MC68HC05X16 is controlled using a block of 30 registers. This comprises 10 control registers, 10 Transmit buffer registers and 10 receive buffer registers ...

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... Freescale Semiconductor, Inc. 5.3.1 MCAN control register (CCNTRL) This register may be read or written to by the MCU; only the RR bit is affected by the MCAN. Address MCAN control (CCNTRL) $0020 MODE SPD MODE — Undefined mode This bit must never be set by the CPU as this would result in the transmit and receive buffers being 5 mapped out of memory ...

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... Freescale Semiconductor, Inc. RIE — Receive interrupt enable 1 (set) – Enabled – The CPU will get an interrupt request whenever a message has been received free of errors. 0 (clear) – Disabled – The CPU will get no receive interrupt request. RR — Reset request When the MCAN detects that RR has been set it aborts the current transmission or reception of a message and enters the reset state ...

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... Freescale Semiconductor, Inc. RX0 — Receive pin 0 (passive) (Refer to 1 (set) – VDD/2 will be connected to the input comparator. The RX0 pin is disconnected. 0 (clear) – The RX0 pin will be connected to the input comparator. VDD/2 is disconnected. RX1 — Receive pin 1 (passive) (Refer to 1 (set) – ...

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... Freescale Semiconductor, Inc. frame sequence (11 recessive bits). The designer must take this into consideration when planning to use the sleep command. COS — Clear overrun status 1 (set) – This clears the read-only data overrun status bit in the CSTAT register (see Section 0 (clear) – ...

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... Freescale Semiconductor, Inc. 5.3.3 MCAN status register (CSTAT) This is a read only register; only the MCAN can change its contents. Address MCAN status $0022 (CSTAT) BS — Bus status This bit is set (off-bus) by the MCAN when the transmit error counter reaches 256. The MCAN will 5 then set RR and will remain off-bus until the CPU clears RR again ...

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... Freescale Semiconductor, Inc. TCS — Transmission complete status This bit is cleared by the MCAN when TR becomes set. When TCS is set it indicates that the last requested transmission was successfully completed. If, after TCS is cleared, but before transmission begins, an abort transmission command is issued then the transmit buffer will be released and TCS will remain clear ...

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... Freescale Semiconductor, Inc. 5.3.4 MCAN interrupt register (CINT) All bits of this register are read only; all are cleared by a read of the register. This register must be read in the interrupt handling routine in order to enable further interrupts. Address MCAN interrupt $0023 (CINT) WIF — Wake-up interrupt fl the MCAN detects bus activity whilst it is asleep, it clears the SLEEP bit in the CCOM register ...

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... Freescale Semiconductor, Inc. RIF — Receive interrupt flag The RIF bit is set by the MCAN when a new message is available in the receive buffer, and the RIE bit in CCNTRL is set. At the same time RBS is set. Like all the bits in this register, RIF is cleared by reading the register, or when reset request is set. ...

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... Freescale Semiconductor, Inc. 5.3.6 MCAN acceptance mask register (CACM) The acceptance mask register specifies which of the corresponding bits in the acceptance code register are relevant for acceptance filtering. Note: This register can only be accessed when the reset request bit in the CCNTRL register is set ...

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... Freescale Semiconductor, Inc. Table 5-1 Synchronization jump width SJW1 BRP5 – BRP0 — Baud rate prescaler bits These bits determine the MCAN system clock cycle time (t individual bit timing, according to BRP5 BRP4 BRP3 osc Divide by OSC1 2 Divide by 10 Figure 5-4 Oscillator block diagram ...

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... Freescale Semiconductor, Inc. 5.3.8 MCAN bus timing register 1 (CBT1) This register can only be accessed when the reset request bit in the CCNTRL register is set. MCAN bus timing 1 (CBT1) SAMP — Sampling This bit determines the number of samples of the serial bus to be taken per bit time. When set three samples per bit are taken ...

Page 79

... Freescale Semiconductor, Inc. Table 5-3 Time segment values TSEG13 TSEG12 TSEG11 TSEG10 Calculation of the bit time BIT_TIME Note: TSEG2 must be at least 2 t samples per bit mode is selected then TSEG2 must be at least 3 t TSEG1 must be at least as long as TSEG2. The synchronization jump width (SJW) may not exceed TSEG2, and must be at least t shorter than TSEG1 to allow for physical propagation delays ...

Page 80

... Freescale Semiconductor, Inc. 5.3.9 MCAN output control register (COCNTRL) This register allows the setup of different output driver configurations under software control. The user may select active pull-up, pull-down, float or push-pull output. Note: This register can only be accessed when the reset request bit in the CCNTRL register is set ...

Page 81

... Freescale Semiconductor, Inc. Normal mode 1 In contrast to biphase mode the bit representation is time invariant and not toggled. Normal mode 2 For the TX0 pin this is the same as normal mode 1, however the data stream to TX1 is replaced by the transmit clock. The rising edge of the transmit clock marks the beginning of a bit time. The clock pulse will be t long ...

Page 82

... Freescale Semiconductor, Inc. 5.3.10 Transmit buffer identifier register (TBI) Transmit buffer identifier (TBI) ID10 – ID3 — Identifier bits The identifier consists of 11 bits (ID10 – ID0). ID10 is the most significant bit and is transmitted first on the bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. The three least signifi ...

Page 83

... Freescale Semiconductor, Inc. DLC3 5.3.12 Transmit data segment registers (TDS) 1 – 8 Address $002C – Transmit data segment (TDS) $0033 DB7 – DB0 — data bits These data bits in the eight data segment registers make up the bytes of data to be transmitted. The number of bytes to be transmitted is determined by the data length code. ...

Page 84

... Freescale Semiconductor, Inc. 5.3.14 Remote transmission request and data length code register (RRTDL) The layout of this register is identical to the TRTDL register (see RTR and data length code (RRTDL) 5.3.15 Receive data segment registers (RDS) 1 – The layout of these registers is identical to the TDSx registers (see ...

Page 85

... Freescale Semiconductor, Inc. Termination network 1.75V 3.25V TX0 680 TX1 680 150k RX0 150k RX1 2 x 30k CANL CANH VDDH MCAN bus lines Figure 5-6 A typical physical interface between the MCAN and the MCAN bus lines MC68HC05X16 MOTOROLA CAN MODULE (MCAN) For More Information On This Product, Go to: www ...

Page 86

... Freescale Semiconductor, Inc. If several CAN modules are driving a dominant level on the bus at the same time then the values for V and V can go to 0.3 and 4.7 volts respectively. The residual 0 due to the CANH CANL voltage drop across the diodes and driver transistors in the transmission circuit. ...

Page 87

... Freescale Semiconductor, Inc. When a dominant level is detected on the MCAN bus, the MCAN is woken up and a wake-up interrupt is generated. Under normal operation the two MCAN bus lines are forced to complementary logic levels. The level of one of the two wires can be disregarded and replaced by V bits, RX0 or RX1. ...

Page 88

... Freescale Semiconductor, Inc. 5 THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA CAN MODULE (MCAN) For More Information On This Product, Go to: www.freescale.com MC68HC05X16 Rev. 1 ...

Page 89

... Freescale Semiconductor, Inc. PROGRAMMABLE TIMER The programmable timer on the MC68HC05X32 consists of a 16-bit read-only free-running counter, with a fixed divide-by-four prescaler, plus the input capture/output compare circuitry. The timer can be used for many purposes including measuring pulse length of two input signals and generating two output signals ...

Page 90

... Freescale Semiconductor, Inc. High Low High byte byte Output $0016 compare compare $0017 register 1 register 2 To PLM 6 Output compare compare circuit 1 circuit ICF1 OCF1 TOF ICF2 Interrupt circuit Input capture interrupt vector $3FF8,9 Figure 6-1 16-bit programmable timer block diagram Internal bus ...

Page 91

... Freescale Semiconductor, Inc. 6.1.1 Counter register and alternate counter register Address Timer counter high $0018 Timer counter low $0019 Address Alternate counter high $001A Alternate counter low $001B The double-byte, free-running counter can be read from either of two locations, $18-$19 (counter register) or $1A-$1B (alternate counter register). A read from only the less significant byte (LSB) of the free-running counter ($19 or $1B) receives the count value at the time of the read read of the free-running counter or alternate counter register fi ...

Page 92

... Freescale Semiconductor, Inc. 6.2 Timer control and status The various functions of the timer are monitored and controlled using the timer control and status registers described below. 6.2.1 Timer control register (TCR) The timer control register ($0012) is used to enable the input captures (ICIE), output compares (OCIE), and timer overfl ...

Page 93

... Freescale Semiconductor, Inc. FOLV2 — Force output compare 2 This bit always reads as zero, hence writing a zero to this bit has no effect. Writing a one at this position will force the OLV2 bit to the corresponding output level latch, thus appearing at the TCMP2 pin. Note that this bit does not affect the OCF2 bit of the status register (see 1 (set) – ...

Page 94

... Freescale Semiconductor, Inc. 6.2.2 Timer status register (TSR) The timer status register ($13) contains the status bits corresponding to the timer interrupt conditions – ICF1, OCF1, TOF, ICF2 and OCF2. Accessing the timer status register satisfies the first condition required to clear the status bits. The remaining step is to access the register corresponding to the status bit ...

Page 95

... Freescale Semiconductor, Inc. ICF2 — Input capture flag 2 This bit is set when a negative edge is detected by the input capture edge detector 2 at TCAP2; an input capture interrupt will be generated if ICIE is set. ICF2 is cleared by reading the TSR and then the input capture low register 2 ($1D). ...

Page 96

... Freescale Semiconductor, Inc. The result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register 1 on each valid signal transition whether the input capture 1 fl ...

Page 97

... Freescale Semiconductor, Inc. 6.4 Output compare ‘Output compare’ technique which may be used, for example, to generate an output waveform signal when a specific time period has elapsed, by presetting the output compare register to the appropriate value. There are two output compare registers: output compare register 1 (OCR1) and output compare register 2 (OCR2) ...

Page 98

... Freescale Semiconductor, Inc. The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read and the write to the corresponding output compare register. All bits of the output compare register are readable and writable and are not altered by the timer hardware or reset ...

Page 99

... Freescale Semiconductor, Inc. The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read and the write to the corresponding output compare register. All bits of the output compare register are readable and writable and are not altered by the timer hardware or reset ...

Page 100

... Freescale Semiconductor, Inc. 6.6 Timer during STOP mode When the MCU enters STOP mode, the timer counter stops counting and remains at that particular count value until STOP mode is exited by an interrupt. If STOP mode is exited by power-on or external reset, the counter is forced to $FFFC but exited by external interrupt (IRQ) then the counter resumes from its stopped value ...

Page 101

... Freescale Semiconductor, Inc. Internal processor clock Internal reset T00 T01 Internal timer clocks T10 T11 16-bit counter External reset or end of POR Note: The counter and timer control registers are the only ones affected by power-on or external reset. Figure 6-2 Timer state timing diagram for reset ...

Page 102

... Freescale Semiconductor, Inc. Internal processor clock Internal timer clocks 16-bit counter Output compare register Compare register latch 6 Output compare flag and TCMP1,2 Note: The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state T01. Thus a four cycle difference may exist between the write to the compare register and the actual compare. ...

Page 103

... Freescale Semiconductor, Inc. SERIAL COMMUNICATIONS INTERFACE A full-duplex asynchronous serial communications interface (SCI) is provided with a standard non-return-to-zero (NRZ) format and a variety of baud rates. The SCI transmitter and receiver are functionally independent and have their own baud rate generator; however they share a common baud rate prescaler and data format ...

Page 104

... Freescale Semiconductor, Inc. Transmit $0011 data register (See note) Transmit TDO data shift pin register 7 Transmitter clock Clock extraction SCLK phase and pin polarity control Note: The serial communications data register (SCI SCDR) is controlled by the internal R/W signal the transmit data register when written to and the receive data register when read ...

Page 105

... Freescale Semiconductor, Inc. 7.2 SCI receiver features • Receiver wake-up function (idle line or address bit) • Idle line detection • Framing error detection • Noise detection • Overrun detection • Receiver data register full flag 7.3 SCI transmitter features • Transmit data register empty flag • ...

Page 106

... Freescale Semiconductor, Inc. When SCDR is read, it contains the last data byte received, provided that the receiver is enabled. The receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has been transferred from the input serial shift register to the SCDR; this will cause an interrupt if the receiver interrupt is enabled ...

Page 107

... Freescale Semiconductor, Inc. 7.5 Data format Receive data or transmit data is the serial data that is transferred to the internal data bus from the receive data input pin (RDI) or from the internal bus to the transmit data output pin (TDO). The non-return-to-zero (NRZ) data format shown in criteria: – ...

Page 108

... Freescale Semiconductor, Inc. 7.6.1 Idle line wake-up In idle line wake-up mode, a dormant receiver wakes up as soon as the RDI line becomes idle. Idle is defined as a continuous logic high level on the RDI line for ten (or eleven) full bit times. Systems using this type of wake-up must provide at least one character time of idle between messages to wake up sleeping receivers, but must not allow any idle time between characters within a message ...

Page 109

... Freescale Semiconductor, Inc. 16X internal sampling clock RT clock edges for all three examples Idle RDI RDI Noise RDI Figure 7-4 SCI examples of start bit sampling technique Previous bit Present bit RDI 16RT 1RT Figure 7-5 SCI sampling technique used on all bits edge will be placed artifi ...

Page 110

... Freescale Semiconductor, Inc. If the receiver detects that a break (RDRF = receiver data register = $0000) produced the framing error, the start bit will not be artificially induced and the receiver must actually detect a logic one before the start bit can be recognised (see Data ...

Page 111

... Freescale Semiconductor, Inc. 7.10 SCI synchronous transmission The SCI transmitter allows the user to control a one way synchronous serial transmission. The SCLK pin is the clock output of the SCI transmitter. No clocks are sent to that pin during start bit and stop bit. Depending on the state of the LBCL bit (bit 0 of SCCR1), clocks will or will not be activated during the last valid data bit (address mark) ...

Page 112

... Freescale Semiconductor, Inc. 7.11 SCI registers The SCI system is configured and controlled by five registers: SCDR, SCCR1, SCCR2, SCSR, and BAUD. 7.11.1 Serial communications data register (SCDR) SCI data (SCDR) The SCDR is controlled by the internal R/W signal and performs two functions in the SCI. It acts as the receive data register (RDR) when it is read and as the transmit data register (TDR) when it is written ...

Page 113

... Freescale Semiconductor, Inc. R8 — Receive data bit 8 This read-only bit is the ninth serial data bit received when the SCI system is configured for nine data bit operation (M = 1). The most significant bit (bit 8) of the received character is transferred into this bit at the same time as the remaining eight bits (bits 0–7) are transferred from the serial receive shift register to the SCI receive data register. T8 — ...

Page 114

... Freescale Semiconductor, Inc. CPOL – Clock polarity This bit allows the user to select the polarity of the clocks to be sent to the SCLK pin. It works in conjunction with the CPHA bit to produce the desired clock-data relation (see Figure 7-10). 1 (set) – Steady high value at SCLK pin outside transmission window. ...

Page 115

... Freescale Semiconductor, Inc. Idle or preceding transmission Start clock (CPOL = 0, CPHA = 0) clock (CPOL = 0, CPHA = 1) clock (CPOL = 1, CPHA = 0) clock (CPOL = 1, CPHA = 1) data 0 Start LSB Figure 7-10 SCI data clock timing diagram (M=1) LBCL – Last bit clock This bit allows the user to select whether the clock associated with the last data bit transmitted (MSB) has to be output to the SCLK pin ...

Page 116

... Freescale Semiconductor, Inc. 7.11.3 Serial communications control register 2 (SCCR2) The SCI control register 2 (SCCR2) provides the control bits that enable/disable individual SCI functions. SCI control (SCCR2) TIE — Transmit interrupt enable 1 (set) – TDRE interrupts enabled. 0 (clear) – TDRE interrupts disabled. ...

Page 117

... Freescale Semiconductor, Inc. After loading the last byte in the serial communications data register and receiving the TDRE flag, the user should clear TE. Transmission of the last byte will then be completed and the line will go idle. 1 (set) – Transmitter enabled. 0 (clear) – Transmitter disabled. ...

Page 118

... Freescale Semiconductor, Inc. 7.11.4 Serial communications status register (SCSR) SCI status (SCSR) The serial communications status register (SCSR) provides inputs to the interrupt logic circuits for generation of the SCI system interrupt. In addition, a noise flag bit and a framing error bit are also contained in the SCSR. ...

Page 119

... Freescale Semiconductor, Inc. OR — Overrun error flag This bit is set when a new byte is ready to be transferred from the receiver shift register to the receiver data register and the receive data register is already full (RDRF bit is set). Data transfer is inhibited until the RDRF bit is cleared. Data in the serial communications data register is valid in this case, but additional data received during an overrun condition (including the byte causing the overrun) will be lost ...

Page 120

... Freescale Semiconductor, Inc. 7.11.5 Baud rate register (BAUD) The baud rate register provides the means to select two different or equivalent baud rates for the transmitter and receiver. SCI baud rate (BAUD) SCP1, SCP0 — Serial prescaler select bits These read/write bits determine the prescale factor, NP, by which the internal processor clock is divided before it is applied to the transmitter and receiver rate control dividers, NT and NR. This common prescaled output is used as the input to a divider that is controlled by the SCR0– ...

Page 121

... Freescale Semiconductor, Inc. SCR2, SCR1, SCR0 — SCI rate select bits (receiver) These three read/write bits select the baud rates for the receiver. The prescaler output described above is divided by the factors shown in Table 7-5 Second prescaler stage (receiver) SCR2 The following equations are used to calculate the receiver and transmitter baud rates: ...

Page 122

... Freescale Semiconductor, Inc. 7.12 Baud rate selection The flexibility of the baud rate generator allows many different baud rates to be selected, depending on the CPU clock frequency. A particular baud rate may be generated by manipulating the various prescaler and division ratio bits. can be achieved for five typical crystal frequencies, for each of the CPU clock frequency options and only using the prescaler bits. obtained using a further division ratio provided by the SCI rate select bits. Note that the fi ...

Page 123

... Freescale Semiconductor, Inc. Table 7-9 SCI transmit baud rate output for a given prescaler output SCT/SCR bits Bit 2 Bit 1 Bit Note: The examples shown in the part is operating in slow mode (see For the receiver, the internal clock frequency is 16 times higher than the selected baud rate ...

Page 124

... Freescale Semiconductor, Inc. 7 THIS PAGE LEFT BLANK INTENTIONALLY SERIAL COMMUNICATIONS INTERFACE For More Information On This Product, Go to: www.freescale.com MC68HC05X16 Rev. 1 ...

Page 125

... Freescale Semiconductor, Inc. PULSE LENGTH D/A CONVERTERS The pulse length D/A converter (PLM) system works in conjunction with the timer to execute two 8-bit D/A conversions, with a choice of two repetition rates. (See PLMA R D/A Latch pin S Zero detector SFA bit Figure 8-1 PLM system block diagram ...

Page 126

... Freescale Semiconductor, Inc. The D/A converter has two data registers associated with it, PLMA and PLMB. Pulse length modulation A (PLMA) Pulse length modulation B (PLMB) This is a dual 8-bit resolution D/A converter associated with two output pins (PLMA and PLMB). The outputs are pulse length modulated signals whose duty cycle ratio may be modified. These signals can be used directly as PLMs, or the fi ...

Page 127

... Freescale Semiconductor, Inc. Note: Since the PLM system uses the timer counter, PLM results will be affected while resetting the timer counter. Both D/A registers are reset to $00 during power-on or external reset. WAIT mode does not affect the output waveform of the D/A converters. ...

Page 128

... Freescale Semiconductor, Inc. 8.2 PLM clock selection The slow/fast mode of the PLM D/A converters is selected by bits 1, 2, and 3 of the miscellaneous register at address $000C (SFA bit for PLMA and SFB bit for PLMB). The slow/fast mode has no effect on the D/A converters’ 8-bit resolution (see ...

Page 129

... Freescale Semiconductor, Inc. ANALOG TO DIGITAL CONVERTER The analog to digital converter system consists of a single 8-bit successive approximation converter and a sixteen channel multiplexer. Eight of the channels are connected to the PD0/AN0 – PD7/AN7 pins of the MC68HC05X16 and the other eight channels are dedicated to internal reference points for test functions ...

Page 130

... Freescale Semiconductor, Inc. The A/D reference input (AN0–AN7) is applied to a precision internal D/A converter. Control logic drives this D/A converter and the analog output is successively compared with the analog input sampled at the beginning of the conversion. The conversion is monotonic with no missing codes. ...

Page 131

... Freescale Semiconductor, Inc. 9.2 A/D registers 9.2.1 Port D data register (PORTD) Address Port D data (PORTD) $0003 Port input-only port which routes the eight analog inputs to the A/D converter. When the A/D converter is disabled, the pins are configured as standard input-only port pins, which can be read via the port D data register ...

Page 132

... Freescale Semiconductor, Inc. 9.2.3 A/D status/control register (ADSTAT) A/D status/control (ADSTAT) COCO — Conversion complete flag 1 (set) – COCO is set each time a conversion is complete, allowing the new result to be read from the A/D result data register ($08). The converter then starts a new conversion. ...

Page 133

... Freescale Semiconductor, Inc. ADON — A/D converter on The ADON bit allows the user to enable/disable the A/D converter. 1 (set) – A/D converter is switched on. 0 (clear) – A/D converter is switched off. When the A/D converter is switched on, it takes a time t (see Table 12-3). During this time A/D conversion results may be inaccurate. ...

Page 134

... Freescale Semiconductor, Inc. 9.4 A/D converter during WAIT mode The A/D converter is not affected by WAIT mode and continues normal operation. In order to reduce power consumption the A/D converter can be disconnected, under software control using the ADON bit and the ADRC bit in the A/D status/control register at $0009, before entering WAIT mode ...

Page 135

... Freescale Semiconductor, Inc. RESETS AND INTERRUPTS 10.1 Resets The MC68HC05X32 can be reset in three ways: by the initial power-on reset function active low input to the RESET pin computer operating properly (COP) watchdog reset. Any of these resets will cause the program its starting address, specified by the contents of memory locations $3FFE and $3FFF, and cause the interrupt mask bit in the condition code register to be set ...

Page 136

... Freescale Semiconductor, Inc. 10.1.1 Power-on reset A power-on reset occurs when a positive transition is detected on VDD. The power-on reset function is strictly for power turn-on conditions and should not be used to detect drops in the power supply voltage. The power-on circuitry provides a stabilization delay (t oscillator becomes active. If the external RESET pin is low at the end of this delay then the processor remains in the reset state until RESET goes high ...

Page 137

... Freescale Semiconductor, Inc. 10.1.3 RESET pin When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied to the RESET input for a minimum period of 1.5 machine cycles (t is used to improve noise immunity on this pin. When the RESET pin goes high, the MCU will resume operation on the following cycle ...

Page 138

... Freescale Semiconductor, Inc. Main CPU clock f /2 osc 4 f /32 prescaler osc running counter) The watchdog system can be automatically enabled, following power-on or external reset, via a mask option (see Section the miscellaneous register at $000C (see cannot be disabled by software (writing a ‘zero’ to the WDOG bit has no effect at any time). In addition, the WDOG bit acts as a reset mechanism for the watchdog counter. Writing a ‘ ...

Page 139

... Freescale Semiconductor, Inc. 10.1.4.1 COP watchdog during STOP mode The STOP instruction is inhibited when the watchdog system is enabled STOP instruction is executed while the watchdog system is enabled, then a watchdog reset will occur as if there were a watchdog timeout. In the case of a watchdog reset due to a STOP instruction, the oscillator will not be affected, thus there will confi ...

Page 140

... Freescale Semiconductor, Inc. Table 10-1 Effect of RESET, POR, STOP and WAIT Timer prescaler cleared Timer counter set to $FFFC All timer enable bits cleared (disable) Data direction registers cleared (inputs) Stack pointer set to $00FF Internal address bus forced to restart Vector $3FFE, $3FFF ...

Page 141

... Freescale Semiconductor, Inc. 10.2 Interrupts The MCU can be interrupted by five different sources: three maskable hardware interrupts, one non maskable software interrupt and one maskable MCAN interrupt: • External signal on the IRQ pin, WOI on port B pins or NWOI pin • Serial communications interface (SCI) • ...

Page 142

... Freescale Semiconductor, Inc. Is I-bit set? IRQ or WOI external interrupt? internal interrupt? internal interrupt? MCAN interrupt? 10 Fetch next instruction Execute instruction Reset NO YES Clear IRQ request latch NO Timer YES NO YES SCI NO YES CIRQ NO Figure 10-4 Interrupt flow chart RESETS AND INTERRUPTS For More Information On This Product, Go to: www ...

Page 143

... Freescale Semiconductor, Inc. 10.2.1 Interrupt priorities Each potential interrupt source is assigned a priority level, which means that if more than one interrupt is pending at the same time, the processor will service the one with the highest priority first. For example, if both an external interrupt and a timer interrupt are pending after an instruction execution, the external interrupt is serviced fi ...

Page 144

... Freescale Semiconductor, Inc. 10.2.3.1 Miscellaneous register Miscellaneous Note: The bits shown shaded in the above representation are explained individually in the relevant sections of this manual. The complete register plus an explanation of each bit can be found in INTP, INTN — External interrupt sensitivity options These two bits allow the user to select which edge the IRQ and WOI pins are sensitive to as shown ...

Page 145

... Freescale Semiconductor, Inc. Note: If the external interrupt function is disabled by the INTE bit and an external interrupt is sensed by the edge detector circuitry, then the interrupt request is latched and the interrupt stays pending until the INTE bit is set. The internal latch of the external interrupt is cleared in the first part of the service routine (except for the low level interrupt which is not latched) ...

Page 146

... Freescale Semiconductor, Inc. Error IRQ: this is set when either the error status or bus status bits in the MCAN status register change state (see Data overrun: an incoming message on the bus cannot be received because both receive buffers are tied up. Wake-up IRQ: this signals activity on the bus while the MCAN is in SLEEP mode. This is the only nonmaskable CIRQ. CIRQ interrupts are serviced by the routine located at the address specifi ...

Page 147

... Freescale Semiconductor, Inc. 10.2.4 Hardware controlled interrupt sequence The following three functions: reset, STOP and WAIT, are not in the strictest sense interrupts. However, they are acted upon in a similar manner. Flowcharts for STOP and WAIT are shown in RESET: A reset condition causes the program to vector to its starting address, which is contained in memory locations $3FFE (MSB) and $3FFF (LSB) ...

Page 148

... Freescale Semiconductor, Inc. THIS PAGE LEFT BLANK INTENTIONALLY 10 RESETS AND INTERRUPTS For More Information On This Product, Go to: www.freescale.com MC68HC05X16 Rev. 1 ...

Page 149

... Freescale Semiconductor, Inc. CPU CORE AND INSTRUCTION SET This section provides a description of the CPU core registers, the instruction set and the addressing modes of the MC68HC05X16. 11.1 Registers The MCU contains five registers, as shown in the programming model of Figure 11-1. The interrupt stacking order is shown in Figure 11-2. ...

Page 150

... Freescale Semiconductor, Inc. Increasing memory address Unstack 11.1.2 Index register (X) The index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. The index register may also be used as a temporary storage area. 11.1.3 Program counter (PC) The program counter is a 16-bit register, which contains the address of the next byte to be fetched ...

Page 151

... Freescale Semiconductor, Inc. Half carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) When this bit is set, all maskable interrupts are masked interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. ...

Page 152

... Freescale Semiconductor, Inc. 11.2.1 Register/memory Instructions Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. ...

Page 153

... Freescale Semiconductor, Inc. Operation Description Condition codes Source Form Table 11-2 Register/memory instructions Immediate Function Load A from memory LDA A6 Load X from memory LDX AE Store A in memory STA Store X in memory STX Add memory to A ADD AB Add memory and carry to A ADC ...

Page 154

... Freescale Semiconductor, Inc. Branch always Branch never Branch if higher Branch if lower or same Branch if carry clear (Branch if higher or same) Branch if carry set (Branch if lower) Branch if not equal Branch if equal Branch if half carry clear Branch if half carry set Branch if plus Branch if minus Branch if interrupt mask bit is clear ...

Page 155

... Freescale Semiconductor, Inc. Table 11-5 Read/modify/write instructions Function Mnemonic Increment INC Decrement DEC Clear CLR Complement COM Negate (two’s complement) NEG Rotate left through carry ROL Rotate right through carry ROR Logical shift left LSL Logical shift right LSR Arithmetic shift right ...

Page 156

... Freescale Semiconductor, Inc. Mnemonic INH ADC ADD AND ASL ASR BCC BCLR BCS BEQ BHCC BHCS BHI BHS BIH BIL BIT BLO BLS BMC BMI BMS BNE BPL BRA BRN BRCLR BRSET BSET 11 BSR CLC CLI CLR CMP Address mode abbreviations ...

Page 157

... Freescale Semiconductor, Inc. Table 11-7 Instruction set (Continued) Mnemonic INH IMM DIR COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR MUL NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STOP STX SUB SWI TAX ...

Page 158

... Freescale Semiconductor, Inc. 11 Table 11-8 M68HC05 opcode map CPU CORE AND INSTRUCTION SET For More Information On This Product, Go to: www.freescale.com MC68HC05X16 Rev. 1 ...

Page 159

... Freescale Semiconductor, Inc. 11.3 Addressing modes Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the memory space. Short indexed accesses are single byte instructions ...

Page 160

... Freescale Semiconductor, Inc. 11.3.4 Extended In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. Instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. When using the Motorola assembler, the user need not specify whether an instruction uses direct or extended addressing ...

Page 161

... Freescale Semiconductor, Inc. 11.3.8 Relative The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of relative addressing is from – ...

Page 162

... Freescale Semiconductor, Inc. THIS PAGE LEFT BLANK INTENTIONALLY 11 CPU CORE AND INSTRUCTION SET For More Information On This Product, Go to: www.freescale.com MC68HC05X16 Rev. 1 ...

Page 163

... Freescale Semiconductor, Inc. ELECTRICAL SPECIFICATIONS This section contains the electrical specifications and associated timing information for the MC68HC05X16. 12.1 Absolute maximum ratings Table 12-1 Absolute maximum ratings Rating (1) Supply voltage Input voltage Input voltage – bootstrap mode (IRQ pin only) ...

Page 164

... Freescale Semiconductor, Inc. 12.2 DC electrical characteristics (V = 5.0 Vdc 10 Characteristic Output voltage I = – LOAD I = +10 A LOAD Output high voltage (I LOAD PA0–7, PB0–7, PC0–7, TCMP1, TCMP2, Output high voltage (I LOAD TDO, SCLK, PLMA, PLMB Output high voltage (I LOAD OSC2 Output low voltage (I LOAD PA0– ...

Page 165

... Freescale Semiconductor, Inc. Table 12-2 DC electrical characteristics (V = 5.0 Vdc 10 Vdc (1) Characteristic Input current OSC1=V (OSC2 Input current OSC1=V (OSC2 Input current IRQ, TCAP1, TCAP2, RDI, PD0/AN0-PD7/AN7 (channel not selected) Capacitance Ports (as input or output), RESET, TDO, SCLK IRQ, TCAP1, TCAP2, OSC1, RDI PD0/AN0– ...

Page 166

... Freescale Semiconductor, Inc. 12.3 A/D converter characteristics (V = 5.0 Vdc 10 Characteristic Resolution Non-linearity Quantization error Absolute accuracy Conversion range ( Conversion time Monotonicity Zero input reading Full scale reading Sample acquisition time Analog input acquisition sampling Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 (3) Input leakage (1) Performance verifi ...

Page 167

... Freescale Semiconductor, Inc. 12.4 Control timing (V = 5.0 Vdc 10 Characteristic Frequency of operation Oscillator frequency MCAN module clock frequency MCU bus frequency Cycle time (see Figure 10-1) Crystal oscillator start-up time (see Stop recovery start-up time (crystal oscillator) A/D converter stabilization time External RESET input pulse width ...

Page 168

... Freescale Semiconductor, Inc. 12.5 MCAN bus interface DC electrical characteristics Table 12-5 MCAN bus interface DC electrical characteristics (V = 5.0 Vdc 10 MCAN bus input comparator: pins RX0 and RX1 Input voltage Common mode range Latch-up trigger current Input offset voltage Hysteresis V 2 generator: pin VDDH ...

Page 169

... PD5/AN5 Device MC68HC05X16, MC68HC05X32 MC68HC705X32 Note: Unless otherwise stated, a pin labelled as ‘NU’ should be tied to V environment. Pins labelled ‘NC’ can be left floating, since they are not bonded to any part of the device. Figure 13-1 64-pin QFP pinout MC68HC05X16 For More Information On This Product, Go to: www ...

Page 170

... Freescale Semiconductor, Inc. 13.2 64-pin quad flat pack (QFP) mechanical dimensions Case No. 840C L 64 lead QFP 0. – 0.05 A – – - Seating Plane Dim. Min. Max. A 13.90 14.10 B 13.90 14.10 C 2.067 2.457 D 0.30 0.45 E 2.00 2.40 F 0.30 — G 0.80 BSC H 0.067 ...

Page 171

... Package Type MC68HC05X16 64-pin QFP MC68HC05X32 64-pin QFP MC68HC705X32 64-pin QFP Note: The high speed version of the MC68HC05X32 has the same device title as the standard version. High speed operation is selected via a check box on the order form and will be confirmed on the listing verification form. See ...

Page 172

... Freescale Semiconductor, Inc. 14.1 EPROMS For the MC68HC05X16, a 16K byte EPROM programmed with the customer’s software (positive logic for address and data) should be submitted for pattern generation. All unused bytes should be programmed to $00. The size of EPROM which should be used for all other family members is ...

Page 173

... Freescale Semiconductor, Inc. MC68HC05X32 Important note The following applies to the D53J MC68HC05X32 mask set only: – Mask options on the MC68HC05X32 allow the customer to select POR delay cycles and oscillator DIV ratio. However, during reset, options of 4064 cycles POR and DIV 10 are forced, regardless of which options the customer has selected ...

Page 174

... Freescale Semiconductor, Inc. Note: The electrical characteristics for the MC68HC05X16 should not be used for the MC68HC05X32. A.2 Memory map, register outline and block diagram VPP1 RESET IRQ OSC2 OSC1 VDD1 VSS1 VDDH TX0 TX1 RX0 RX1 NWOI MDS VDD VSS PD0/AN0 ...

Page 175

... Freescale Semiconductor, Inc. MC68HC05X32 $0000 I/O and registers (32 bytes) $0020 MCAN registers (30 bytes) $003E $0050 RAM I (176 bytes) $00C0 Stack $0100 OPTR (1 byte) $0101 Non protected (31 bytes) $0120 EEPROM (256 bytes) Protected (224 bytes) $0200 Bootstrap ROM I (80 bytes) $0250 RAM II ...

Page 176

... Freescale Semiconductor, Inc. Register $0000 Ports 7 bytes $0007 EEPROM/ECLK control 1 byte $0008 A/D converter 2 bytes $000A PLM system 2 bytes $000C Miscellaneous 1 byte $000D SCI 5 bytes $0012 Timer 14 bytes $0020 MCAN control registers 10 bytes $002A MCAN transmit buffer 10 bytes $0034 MCAN receive buffer ...

Page 177

... Freescale Semiconductor, Inc. Register name Address bit 7 Port A data (PORTA) $0000 Port B data (PORTB) $0001 Port C data (PORTC) $0002 Port D data (PORTD) $0003 Port A data direction (DDRA) $0004 Port B data direction (DDRB) $0005 Port C data direction (DDRC) $0006 EEPROM/ECLK control $0007 ...

Page 178

... Freescale Semiconductor, Inc. A.3 Electrical specifications This section contains the electrical specifications and associated timing information for the MC68HC05X32. A.3.1 Maximum ratings Supply voltage Input voltage Input voltage – bootstrap mode (IRQ pin only) Operating temperature range Storage temperature range ...

Page 179

... Freescale Semiconductor, Inc. A.3.2 DC electrical characteristics Table A-3 DC electrical characteristics (V = 5.0 Vdc 10 Vdc (1) Characteristic Output voltage I = – LOAD I = +10 A LOAD Output high voltage (I = 0.8mA) LOAD PA0–7, PB0–7, PC0–7, TCMP1, TCMP2, Output high voltage (I = 1.6mA) LOAD TDO, SCLK, PLMA, PLMB Output high voltage (I = – ...

Page 180

... Freescale Semiconductor, Inc 5.0 Vdc 10 Characteristic Input current OSC1=V (OSC2=V DD Input current OSC1=V (OSC2=V SS Input current IRQ, TCAP1, TCAP2, RDI, PD0/AN0-PD7/AN7 (channel not selected) Capacitance Ports (as input or output), RESET, TDO, SCLK IRQ, TCAP1, TCAP2, OSC1, RDI PD0/AN0–PD7/AN7 (A/D off) PD0/AN0–PD7/AN7 (A/D on) ...

Page 181

... Freescale Semiconductor, Inc. A.3.3 A/D converter characteristics (V = 5.0 Vdc 10 Vdc – +125 Characteristic Resolution Number of bits resolved by the A/D Non-linearity Max deviation from the best straight line through the A/D transfer characteristics ( and Quantization error Uncertainty due to converter resolution Absolute accuracy ...

Page 182

... Freescale Semiconductor, Inc. A.3.4 Control timing (V = 5.0 Vdc 10 Frequency of operation Oscillator frequency MCAN module clock frequency MCU bus frequency Cycle time (see Crystal oscillator start-up time (see Stop recovery start-up time (crystal oscillator) A/D converter stabilization time External RESET input pulse width ...

Page 183

... Freescale Semiconductor, Inc. External signal (TCAP1, TCAP2) A.3.5 MCAN bus interface DC electrical characteristics Table 1-6 MCAN bus interface DC electrical characteristics (V = 5.0 Vdc 10 Characteristic MCAN bus input comparator: pins RX0 and RX1 Input voltage Common mode range Latch-up trigger current Input offset voltage ...

Page 184

... Freescale Semiconductor, Inc. A.3.6 MCAN bus interface control timing characteristics Table 1-7 MCAN bus interface control timing characteristics (4. MCAN bus output driver Rise and fall time (C 15 5.5V Vdc – +125 Characteristic Symbol = 100pF) T LOAD RF MC68HC05X32 For More Information On This Product, Go to: www ...

Page 185

... B-10) is 1.5 t – Maximum bus speed 2.2 MHz The MC68HC705X32 is a device similar to the MC68HC05X16, but with 32K bytes of EPROM instead of 16K bytes of ROM. In addition, the bootstrap routines available in the MC68HC05X16 are replaced by bootstrap routines specific to the MC68HC705X32. The entire MC68HC05X16 data sheet applies to the MC68HC705X32, with the exceptions outlined in this appendix ...

Page 186

... Note: Although this pin can be left floating to disconnect the MCAN module advisable to connect it to VSS when the module is not in use. 15 Section B.9.2 and Section B.9.5 MC68HC705X32 For More Information On This Product, Go to: www.freescale.com contain data specific to this device. MC68HC05X16 Rev. 1 ...

Page 187

... VSS PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 8-bit PD4/AN4 A/D converter PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL Figure B-1 MC68HC705X32 block diagram MC68HC05X16 For More Information On This Product, Go to: www.freescale.com 31248 bytes EPROM (including 16 bytes user vectors) 32 654 bytes bootstrap ROM MCAN 528 bytes ...

Page 188

... WOI DIV2 DIV8 RTIM MC68HC705X32 For More Information On This Product, Go to: www.freescale.com State on bit 3 bit 2 bit 1 bit 0 Undefined Undefined PC2/ECLK Undefined PD3 PD2 PD1 PD0 Undefined ...

Page 189

... Timer output compare 1& 2 $7FF8–9 Timer input capture 1& 2 $7FFA–B WOI, External IRQ $7FFC–D SWI $7FFE–F Reset/power-on reset Figure B-2 Memory map of the MC68HC705X32 MC68HC05X16 For More Information On This Product, Go to: www.freescale.com EPROM User Vectors MC68HC705X32 Register groups ...

Page 190

... MCAN receive buffer 10 bytes $003E $0047 $0100 Options register $7FDE Mask options register Figure B-2 Memory map of the MC68HC705X32 (Continued) 15 MC68HC705X32 For More Information On This Product, Go to: www.freescale.com Registers $0000 Port A data register $0001 Port B data register $0002 Port C data register ...

Page 191

... Freescale Semiconductor, Inc. B.5 EPROM The MC68HC705X32 memory map is given in of EPROM. 16 bytes are used for the reset and interrupt vectors from address $7FF0 to $7FFF. The main EPROM block of 31232 bytes is located from $0400 to $7DFF. One byte of EPROM is used as an option register and is located at address $7FDE. ...

Page 192

... WOIE CAF E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000 Section 5.5). The bit is cleared when the MCAN wakes up. MC68HC705X32 For More Information On This Product, Go to: www.freescale.com switching must PP6 State bit 3 bit 2 bit 1 bit 0 on reset Section B ...

Page 193

... A programming operation will take place. Once the program/erase EEPROM address has been selected, E1ERA cannot be changed. MC68HC05X16 For More Information On This Product, Go to: www.freescale.com programming time, the E6LAT bit has to be reset PROG1 Description 0 Read/execute in EPROM 0 Ready to write address/data to EPROM 1 programming in progress MC68HC705X32 15 B-9 ...

Page 194

... Table B-3 EEPROM1 control bits description E1LAT E1PGM Description 0 0 Read condition 1 0 Ready to load address/data for program/erase 1 1 Byte programming in progress 1 0 Ready for byte erase (load address Byte erase in progress MC68HC705X32 For More Information On This Product, Go to: www.freescale.com MC68HC05X16 Rev. 1 ...

Page 195

... EEPROM/EPROM not protected. 0 (clear) – EEPROM/EPROM protected. MC68HC05X16 For More Information On This Product, Go to: www.freescale.com bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 MC68HC705X32 State bit 1 bit 0 on reset EE1P SEC Not affected 15 B-11 ...

Page 196

... Clock divide ratio where the RESET pin is kept low after a power-on reset. PORL = 16 cycles. PORL = 4064 cycles. PORL MC68HC705X32 For More Information On This Product, Go to: www.freescale.com bit 4 bit 3 bit 2 bit 1 bit 0 RTIM RWAT WWAT PBPD PCPD Not affected Table B-4). Note that ...

Page 197

... Pull-down resistors are connected to all 8 pins of port C; the pull-down (clear) – No pull-down resistors are connected. MC68HC05X16 For More Information On This Product, Go to: www.freescale.com , is active only while the pin is an input active only while the pin is an input. PD MC68HC705X32 15 B-13 ...

Page 198

... The hold time on the IRQ, MDS, TCAP1 and TCAP2 pins is two clock cycles after the external RESET pin is brought high. When the MC68HC705X32 is placed in the bootstrap mode, the bootstrap reset vector will be fetched and the bootstrap firmware will start to execute. to enter each level of bootstrap mode on the rising edge of RESET . ...

Page 199

... For More Information On This Product, Go to: www.freescale.com Parallel E/EEPROM bootstrap Erased EPROM verification Y Y SEC bit active? Red LED PD4 set Jump to RAM PD2 set? N Reserved for Motorola use Y SEC bit active? Red LED PD4 set MC68HC705X32 Serial RAM load/execute ($0051) 15 B-15 ...

Page 200

... Base address = $400 Base address = $100 (EPROM only) (EPROM and EEPROM) A PD2 set Base address = $100 (EPROM and EEPROM) N Data verified? Y Green LED on MC68HC705X32 For More Information On This Product, Go to: www.freescale.com Y Base address = $400 (EPROM only) Red LED on MC68HC05X16 Rev. 1 ...

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