CA3081F Intersil Corporation, CA3081F Datasheet

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CA3081F

Manufacturer Part Number
CA3081F
Description
General purpose high current NPN transistor arrays
Manufacturer
Intersil Corporation
Datasheet

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December 1992
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• High Voltage Types (20V Rating)
• Decoded 7 Segment Display Outputs and Ripple
• Counter and 7 Segment Decoding in One Package
• Easily Interfaced with 7 Segment Display Types
• Fully Static Counter Operation DC to 6MHz (typ.) at VDD =
• Ideal for Low-Power Displays
• “Ripple Blanking” and Lamp Test
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Schmitt-Triggered Clock Inputs
• Meets All Requirements of JEDEC Tentative Stan-
Applications
• Decade Counting 7 Segment Decimal Display
• Frequency Division 7 Segment Decimal Displays
• Clocks, Watches, Timers (e.g.
• Counter/Display Driver For Meter Applications
Pinout
Blanking
10V
dards No. 13B, “Standard Specifications for Descrip-
tion of “B” Series CMOS Device’s
Display
RIPPLE BLANKING OUT
RIPPLE BLANKING IN
CLOCK INHIBIT
CARRY OUT
CLOCK
VSS
CD4033BMS
g
f
TOP VIEW
1
2
3
4
5
6
7
8
60,
16
15
14
13
12
11
10
60, 12 Counter/
9
VDD
RESET
LAMP TEST
c
b
e
a
d
7-826
Description
CD4033BMS consists of a 5 stage Johnson decade counter
and an output decoder which converts the Johnson code to a 7
segment decoded output for driving one stage in a numerical
display.
This device is particularly advantageous in display applications
where low power dissipation and/or low package count is
important.
A high RESET signal clears the decade counter to its zero
count. The counter is advanced one count at the positive clock
signal transition if the CLOCK INHIBIT signal is low. Counter
advancement via the clock line is inhibited when the CLOCK
INHIBIT signal is high. The CLOCK INHIBIT signal can be used
as a negative-edge clock if the clock line is held high. Antilock
gating is provided on the JOHNSON counter, thus assuring
proper counting sequence. The CARRY-OUT (Cout) signal
completes one cycle every ten CLOCK INPUT cycles and is
used to clock the succeeding decade directly in a multi-decade
counting chain.
The seven decoded outputs (a, b, c, d, e, f, g) illuminate the
proper segments in a seven segment display device used for
representing the decimal numbers 0 to 9. The 7 segment out-
puts go high on selection.
Functional Diagram
CD4033BMS
CLOCK
INHIBIT
RIPPLE
BLK
IN
CLOCK
RESET
LAMP
TEST
CMOS Decade Counter/Divider
14
15
1
2
3
VDD
VSS
16
8
10
12
13
9
11
6
7
5
4
RIPPLE
BLK
OUT
a
b
c
d
e
g
CARRY OUT
f
File Number
3301

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CA3081F Summary of contents

Page 1

... VSS 8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD4033BMS Description CD4033BMS consists stage Johnson decade counter and an output decoder which converts the Johnson code segment decoded output for driving one stage in a numerical display ...

Page 2

The CD4033BMS has provisions for automatic blanking of the non-significant zeros in a multi-digit decimal number which results in an easily readable display consistent with normal writing practice. For example, the number 0050.0700 in an eight digit display would be ...

Page 3

Absolute Maximum Ratings DC Supply Voltage Range, (VDD -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . ...

Page 4

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) Propagation Delay TPHL1 VDD = 5V, VIN = VDD or GND Clock To Carry Out TPLH1 Propagation Delay TPHL2 VDD = 5V, VIN = VDD or GND Clock ...

Page 5

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL ...

Page 6

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Propagation Delay Time TPHL VDD = 5V TPLH NOTES: 1. All voltages referenced to device GND 50pF 200K, Input TR, TF < 20ns. TABLE 5. BURN-IN ...

Page 7

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS FUNCTION OPEN GROUND Static Burn- 14, 15 Note 1 Static Burn- Note 1 Dynamic Burn- ...

Page 8

Typical Performance Characteristics AMBIENT TEMPERATURE ( + GATE-TO-SOURCE VOLTAGE (VGS) = 15V 10V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 4. TYPICAL N-CHANNEL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS ...

Page 9

Typical Performance Characteristics 20 AMBIENT TEMPERATURE ( + 20ns SUPPLY VOLTAGE (VDD) (V) FIGURE 10. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY AS A FUNCTION ...

Page 10

Display Devices VDD CD4033BMS CLOCK 7 INHIBIT SEGMENTS RESET VSS LOW-POWER INCANDESCENT READOUTS PINLITES INC-Series O and R TUBE REQUIREMENTS VT(V) 0-03-15 1.5 0-04-30 3 0-06-30 3 R-R3-20 2 R-R4-30 3 *The interfacing buffers shown, while a necessity with ...

Page 11

... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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