CY82C693UB-NC Cypress Semiconductor Corporation., CY82C693UB-NC Datasheet
CY82C693UB-NC
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CY82C693UB-NC Summary of contents
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... DRAMControl DRAM PCI LOCAL BUS Data[0:31] CY82C693UB USB Bus ISA Bus • 3901 North First Street • San Jose CY82C693UB Controller with USB support for the PCI and ISA bus interfaces CY82C692 CACHE DRAM Data[32:63] DRAM DRAM Upper 4 bytes Lower 4 Bytes ...
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... Features ................................................................................................................................................... 1 CY82C693UB Signals ........................................................................................................................... 11 Pin Configuration ................................................................................................................................... 12 CY82C693UB Pin Reference (In Numerical Order by Pin Number) ...................................................... 13 CY82C693UB Pin Reference (In Alphabetical Order by Signal Name) ................................................. 14 Introduction ............................................................................................................................................ 17 System Overview ............................................................................................................................................. 17 CY82C693UB Introduction .............................................................................................................................. 17 Functional Overview .............................................................................................................................. 17 PCI Bus Interface ............................................................................................................................................ 17 ISA Bus Interface ............................................................................................................................................. 18 Reset Logic ...................................................................................................................................................... 18 Keyboard Controller ......................................................................................................................................... 19 Operating Frequency ....................................................................................................................................................19 Resetting the Keyboard Controller ...............................................................................................................................19 Host Interface ...
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... Register 4F: Throttle Timer DMA Request Detection Control #1 (Read/Write) - Index=4FH ......................... 52 Register 50: Non-motherboard Memory Address Range Decode for Event Detection Register #1 (Read/Write) - Index=50H ........................................................................................................... 52 Register 51: Non-motherboard Memory Address Range Decode for Event Detection Register #2 (Read/Write) - Index=51H ........................................................................................................... 52 Register 52: Non-motherboard Memory Address Mask for Event Detection Register #1 (Read/Write) - Index=52H ............................................................................................................................... 52 PRELIMINARY TABLE OF CONTENTS (continued) 3 CY82C693UB ...
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... Port 92: PS/2 Reset Control (Read/Write) - I/O Address=092H ...................................................................... 70 Port B2: APM Control Port (Read/Write) - I/O Address=0B2H ........................................................................ 71 Port B3: APM Status Port (Read/Write) - I/O Address=0B3H ......................................................................... 71 CY82C693UB DMA Controller Registers .............................................................................................. 72 DMA Register 0: DMAC1 Channel 0 Current Address Register (Read/Write) - I/O Address=000H ............... 72 DMA Register 1: DMAC1 Channel 0 Current Word Count Register (Read/Write) - I/O Address=001H ......... 72 DMA Register 2: DMAC1 Channel 1 Current Address Register (Read/Write) - I/O Address=002H ...
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... DMA Register 32: DMAC1 Channel 2 Page Address Register (Read/Write) - Index=081H ........................ 84 DMA Register 33: DMAC1 Channel 3 Page Address Register (Read/Write) - Index=082H ........................ 84 DMA Register 34: DMAC1 Channel 1 Page Address Register (Read/Write) - Index=083H ........................ 84 DMA Register 35: DMAC1 Channel 0 Page Address Register (Read/Write) - Index=087H ........................ 84 DMA Register 36: DMAC2 Channel 6 Page Address Register (Read/Write) - Index=089H ........................ 84 TABLE OF CONTENTS (continued) 5 CY82C693UB ...
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... DMA Register 46: DMAC2 Channel 5 High Page Address Register (Read/Write) - Index=48BH ............... 86 DMA Register 47: DMAC2 Extended Mode Control (Write Only) - I/O Address=4D6H .................................. 86 DMAC2 Extended Mode Control Register Format .......................................................................................... 86 CY82C693UB IDE (Bus Mastering) DMA Controller Registers ............................................................. 87 SFF-8038i Registers ........................................................................................................................................ 87 Bus Master IDE Command Register Format (Offset+00H for Primary Channel; ...
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... Keyboard to System Command Set .............................................................................................................. 109 System to Mouse Controller Command Set .................................................................................................. 110 Mouse to System Controller Command Set .................................................................................................. 111 CY82C693UB PCI Configuration Registers ......................................................................................... 112 PCI to ISA PCI Configuration Registers (Function 0 during Configuration Cycle) ............................... 112 Register 0: Vendor ID Number (Read Only) - Index=00H with a 16-bit access ............................................ 112 Register 1: Device ID Number (Read Only) - Index=02H with a 16-bit access ...
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... Index=4DH with an 8-bit access .................................................................................................................. 120 Register 24: CY82C693UB USB Control Register 1 (Read/Write) - Index=4EH with an 8-bit access .......... 121 Register 24: CY82C693UB USB Control Register 2 (Read/Write) - Index=4FH with an 8-bit access .......... 121 Primary Channel IDE PIO (Programmed I/O) PCI Configuration Registers (Function 1 during Configuration Cycle) ................................................. 122 Register 0: Vendor ID Number (Read Only) - Index=00H with a 16-bit access ...
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... Register 2: HcCommandStatus (Read/Write) - Offset=08H with a 32-bit access .......................................... 138 Register 3: HcInterruptStatus (Read/Write) - Offset=0CH with a 32-bit access ............................................ 138 Register 4: HcInterruptEnable (Read/Write) - Offset=10H with a 32-bit access ............................................ 139 Register 5: HcInterruptDisable (Read/Write) - Offset=14H with a 32-bit access ........................................... 140 Register 6: HcHCCA (Read/Write) - Offset=18H with a 32-bit access .......................................................... 140 PRELIMINARY TABLE OF CONTENTS (continued) 9 CY82C693UB ...
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... Register 22: HceInput - Index=104H with a 32-bit access ............................................................................. 147 Register 23: HceOutput - Index=108H with a 32-bit access .......................................................................... 147 Register 24: HceStatus (Read/Write) - Index=10CH with a 32-bit access .................................................... 147 Maximum Ratings ................................................................................................................................ 148 Electrical Characteristics ...................................................................................................................... 148 Switching Waveforms .......................................................................................................................... 149 Ordering Information ............................................................................................................................ 163 Package Diagrams .............................................................................................................................. 164 PRELIMINARY TABLE OF CONTENTS (continued) 10 CY82C693UB ...
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... CY82C693UB Signals AD[31:0] PCICLK C/BE[3:0] FRAME IRDY TRDY DEVSEL PAR STOP SERR IDSEL INTA INTB INTC INTD GNTBSY/GRANT FREQACK/IRQ8 REQ[3:0]/PGNT/SGNT GNT[3:0]/PREQ/SREQ IRQ8/PSRSTB VCCBAT [1] X2/RTCRD [2] X1/RTCWT ROMCS/ROMMODE SMI/GBSEP STOPCLK/RSTCHG EPMI PWGD CPURST PCIRST INIT USB_CLK USB_D1+/USB_D1 USB_D2+/USB_D2 NOTES: 1. RTCRD available only as bond option. ...
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... PRELIMINARY 208-pin PQFP Top View CY82C693UB 12 CY82C693UB 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 ...
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... CY82C693UB Pin Reference (In Numerical Order by Pin Number) Pin Pin # Pin Name # Pin Name 1 GND 43 AD9 2 FRAME 44 AD8 3 IDSEL 45 AD7 4 TRDY 46 AD6 5 IRDY 47 AD5 6 DEVSEL 48 AD4 7 SERR 49 AD3 8 PAR 50 AD2 9 USB_D1+ 51 AD1 10 USB_D1– 52 AD0 11 C/BE3 53 GND 12 C/BE2 54 IOCHK 13 C/BE1 55 IOCHRDY 14 C/BE0 ...
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... CY82C693UB Pin Reference (In Numerical Order by Pin Number) Pin Pin # Pin Name # Pin Name 35 AD16 77 SA14/IDE10 36 AD15 78 SA13/IDE9 37 AD14 79 SA12/IDE8 38 AD13 80 SA11/IDE7 39 AD12 81 GND 40 AD11 82 SA10/IDE6 41 AD10 83 SA9/IDE5 42 GND 84 SA8/IDE4 CY82C693UB Pin Reference (In Alphabetical Order by Signal Name) Pin Pin Name No. Pin Name Pin No ...
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... CY82C693UB Pin Reference (In Alphabetical Order by Signal Name) Pin Pin Name No. Pin Name Pin No. AD21 28 FREQACK/ 190 IRQ8 AD22 27 GND 1, 21, 33, 42, 53, 67, 71, 81, 93, 105, 125, 137, 151, 171,197 AD23 26 GNT0/PREQ 191 AD24 25 GNT1/SREQ 192 AD25 24 GNT2/SQWV 193 AD26 23 GNT3/DISARB 194 AD27 ...
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... PRELIMINARY Reset Circuitry Power Management Logic ROM/Flash XD Control Bus USB Bus USB Host Controller PCI Bus IDE Controller Figure 1. CY82C693UB Functional Block Diagram To Keyboard Connector Keyboard Controller Timer/Counter Pre-Read/ Post-write Buffers PCI Interface PCI Arbiter (can be disabled) 16 CY82C693UB DMA Controllers AT Refresh ...
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... IRDY or the target deasserts TRDY. A transaction is terminated by the deassertion of FRAME prior to the final data phase PCI master, the CY82C693UB will only perform memory read and write transactions. A read or write cycle consists of a maximum of 4 bytes of data in a single data cycle ...
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... If no transfer parameters are stored, then the request is a normal ISA transfer. If the ISA request is a DMA transfer, the CY82C693UB outputs the pre-programmed starting address and the control signals onto the ISA bus. It will also assert AEN to the requesting ISA bus master so that it will ignore the address and simply provide the data to be transferred onto the ISA bus ...
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... PCI clock cycles. A “warm” reset is performed whenever the CPU writes Port 92H, bit 0, to “1”. The keyboard controller within the CY82C693UB can also issue a fast “warm” reset if the user writes FE (hex) to port 64 (hex). INIT provides CPURST functionality except INIT leaves the CPU’s level 1 cache, internal write-buffers, and floating-point registers intact ...
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... When any of the timers ex- pire, the CY82C693UB will assert SMI (until it is cleared in the handler) and set a configuration register bit to indicate which timer(s) expired. The System Management Interrupt handler must read status registers to determine the source of the SMI ...
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... The first thing the DMACs do, after entering the ACTIVE state, is arbitrate for the PCI bus. The CY82C693UB must obtain ownership of the PCI bus regardless of whether the target is on PCI or not. After the PCI bus has been won, the CY82C693UB will issue DMA acknowledge to the highest pri- ority requestor ...
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... AT interrupt priorities. Inter- rupt arbitration can be programmed to be rotating or fixed. When interrupt requests come in from the system, the CY82C693UB will store all requests, evaluate the priority, and respond with the appropriate acknowledge vector for the CPU’s first interrupt acknowledge cycle. Then, if automatic ...
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... PCI bus. If GNTBSY is not sampled asserted in the next clock cycle after the original deassertion, the CY82C693UB will grant the PCI bus to the highest priority requesting master. However, if GNTBSY is reasserted by the CPU-to-PCI bridge, the CY82C693UB will not grant the bus to any other PCI masters until GNTBSY is deasserted again by the CPU-to-PCI bridge ...
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... PWGD. After PWGD goes active, the PCIRST input can be driven active by an external agent to reset the internal circuitry of the CY82C693UB. PCIRST will also be inverted and driven out on the CPURST output. ISA bus is also reset by the asser- tion of PCIRST. PCIRST is a synchronous input (sampled on PCI clock) ...
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... CPU Reset: This signal resets the CPU and the ISA bus. PCI Reset: This signal functions as the PCI bus reset. During normal operation, this signal is an output only (used by the CY82C693UB to reset PCI bus residents). If pin 172 is pulled LOW through a 1K Ohm resistor, PCIRST becomes an input that is used to initiate a CY82C693UB reset and an ISA reset ...
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... BUSY to the central arbiter. BUSY tells the CY82C693UB that the CY82C691 owns the PCI bus. The CY82C693UB will not grant the PCI bus to any other PCI master until BUSY is deas- serted by the CY82C691. When no requests are pending on the PCI bus, this signal reverts to 691 GRANT and is driven active (LOW) to allow the CY82C691 to take possession of the PCI bus ...
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... If the internal PCI arbiter is disabled (by strapping pin 194 LOW through a 1K Ohm resistor), this signal becomes the PREQ output. PREQ is driven active by the CY82C693UB to request ownership of the PCI bus for ISA or IDE DMA and USB Host Controller (if no separate arbitration used) cycles. ...
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... If pin 179 is strapped LOW during power-up (GNTBSY split), this signal becomes the BUSY input. BUSY is asserted by the CPU-to-PCI bridge to tell the PCI arbiter in the CY82C693UB that the PCI bus is currently busy and may not be granted to any other PCI master. XD Bus, Bit 5/IDE DMA Request 0: If zero TTL is desired for XD bus support (BIOS ROM data, external keyboard controller data, and external RTC data), this is bit 5 of the data bus ...
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... Ohm resistor to ground if PS/2 keyboard support is desired. Non-maskable CPU Interrupt: This is the NMI (non-maskable interrupt request) signal that is connected directly to the CPU’s NMI pin. When the CY82C693UB detects a fatal error (such as a PCI parity error), it will assert NMI to the CPU. ...
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... TTL decoder. ISA DMA/Master 6 Acknowledge Input/Internal Real Time Clock Enable/General Pur- pose I/O 10: This signal is used by the CY82C693UB to grant ISA bus mastership to external ISA peripherals for DMA or ISA MASTER cycles. At power-up, this pin should be pulled-down through a 1K Ohm resistor to disable the internal RTC if an external RTC is desired ...
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... Speaker Output: This signal is the output of counter 2 in the timer/counter logic. It can be used to drive a speaker. End of Process: This signal is driven by the CY82C693UB to signal the end of a block transfer during a DMA cycle. Ignore Numerical Error: This signal is driven by the CY82C693UB to the CPU and should be connected to the CPU’ ...
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... Memory Chip Select: This signal is driven active by any ISA MEMORY target that can support 16-bit accesses. During ISA Master cycles, the CY82C693UB will drive this signal. System Byte High Enable: This signal is driven active by the current ISA bus master to indicate that valid data resides on SD[15:8] ...
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... STOPCLK/RSTCHG is strapped LOW through an external 1K Ohm resistor, PCIRST becomes an input. When PCIRST is sampled asserted, all registers/FIFOs/state within the CY82C693UB are cleared to a known reset state. CPURST is driven active for the duration of PCIRST active. There is no minimum guaranteed assertion time for CPURST in this mode. ...
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... This is the +3.3V power supply pin for the device. It should be maintained CC within the proper operating limits. GROUND: These are the 0V power supply pins for the device. They should be main- tained within the proper operating limits. 34 CY82C693UB Result X No ROM address bits are inverted. (EPROM or boot- block recovery mode). ...
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... Extended System Memory Conventional System BIOS Extended System BIOS Peripheral BIOS (Block D) Peripheral BIOS (Block C) Video Memory (Block B) Video Memory (Block A) Extended System Memory Conventional System Memory Figure 5. hyperCache Memory Map Diagram 35 CY82C693UB FFFFFFFF FFFF0000 FFFEFFFF FFFE0000 FFFDFFFF FFF00000 FFEFFFFF 00100000 000FFFFF 000F0000 ...
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... DMA Page Registers Real Time Clock Registers Keyboard Control & Port B Registers Timer/Counter Config. Registers Chipset Configuration Data Port Chipset Configuration Address Port Interrupt Controller 1 Registers DMA Controller 1 Registers Figure 6. hyperCache CY82C693UB I/O Map Diagram 36 CY82C693UB FFFFFFFF 00010000 0000FFFF 000004D7 000004D6 ...
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... CY82C693UB Control Registers The control registers for the CY82C693UB are defined in this section. The registers can be accessed through I/O Ports 22H and 23H (PCI I/O Reads or Writes to address 22H and 23H). To access each register, the user must first write the index Register 1: Peripheral Configuration Register #1 (Read/Write) — ...
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... Register 3: Interrupt Request Level/Edge Control Register #1 (Read/Write) Bit Function 7 IRQ7 Edge-Triggered/Level-Sensitive Selector: 0: Edge-Triggered 1: Level-Sensitive 6 IRQ6 Edge-Triggered/Level-Sensitive Selector: 0: Edge-Triggered 1: Level-Sensitive 5 IRQ5 Edge-Triggered/Level-Sensitive Selector: 0: Edge-Triggered 1: Level-Sensitive 4 IRQ4 Edge-Triggered/Level-Sensitive Selector: 0: Edge-Triggered 1: Level-Sensitive 3 IRQ3 Edge-Triggered/Level-Sensitive Selector: 0: Edge-Triggered 1: Level-Sensitive 2:0 Reserved PRELIMINARY Index=02H 38 CY82C693UB Default 000 Index=03H Default 000 ...
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... Value programmed into this register is used to fine-tune the 32-kHz Oscillator for greater RTC accuracy. The frequency variation is not linear and changes as the following: 000: +16 ppm 011: 0 ppm 111: 14 ppm Each on bit adds 0 capacitance onto the crystal pins internally. PRELIMINARY Index=05H 39 CY82C693UB Index=04H Default Default ...
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... This register contains the shadowed value that was written into DMA2’s write request register. (DMA Register 25) PRELIMINARY read, mask-off, and then modify certain fields within the write-only registers. Index=80H Index=82H Index=83H Index=84H Index=85H Index=88H 40 CY82C693UB Default 00000000 Index=81H Default 00000000 Default 00000000 Default 00000000 Default 00000000 ...
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... Register 8F: Extended CMOS RAM address Shadow Register (Read/Write) Bit Function 7:0 This register contains the shadowed value that was written into the extended CMOS RAM address register. PRELIMINARY Index=8AH Index=8BH Index=8CH Index=8DH Index=8EH 41 CY82C693UB Index=89H Default 00000000 Default 00000000 Default 00000000 Default 00000000 Default 00000000 Default ...
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... The following registers control the operation of GPIO. Register 90: General Purpose I/O Control Register A (Read/Write) Bit Function 7 Internal Keyboard Controller GPIO Port Output Control: 0: Internal Keyboard Controller Ports not available on outputs of the CY82C693UB. 1: Internal Keyboard Controller Ports available on outputs of the CY82C693UB. 6 Reserved 5 GPIO5 Control: This bit value will be driven onto the GPIO5 pin programmed as an output ...
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... Register 93: General Purpose I/O Input/Output Control Register B (Read/Write) Bit Function 7:6 Reserved 5 GPIO11 Control: 0: Input 1: Output 4 GPIO10 Control: 0: Input 1: Output 3 GPIO9 Control: 0: Input 1: Output 2 GPIO8 Control: 0: Input 1: Output 1 GPIO7 Control: 0: Input 1: Output 0 GPIO6 Control: 0: Input 1: Output PRELIMINARY Index=92H 43 CY82C693UB Default Index=93H Default ...
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... Power Management Control Registers The following registers control the operation of the power man- agement logic within the CY82C693UB. Register 40: Standby Timer Event Detection Control (Read/Write) Bit Function 7 PCI Master Request Detection Control: 0: Disable PCI Master Request Detection 1: Enable PCI Master Request Detection ...
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... IRQ11 Monitor Control: 0: Disable IRQ11 Monitoring 1: Enable IRQ11 Monitoring 2 IRQ10 Monitor Control: 0: Disable IRQ10 Monitoring 1: Enable IRQ10 Monitoring 1 IRQ9 Monitor Control: 0: Disable IRQ9 Monitoring 1: Enable IRQ9 Monitoring 0 IRQ8 Monitor Control: 0: Disable IRQ8 Monitoring 1: Enable IRQ8 Monitoring PRELIMINARY 45 CY82C693UB Index=41H Default Index=42H Default ...
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... Enable Hard Disk Access Detection 1 Floppy Disk Access (3f5H) Detection Control: 0: Disable Floppy Disk Access Detection 1: Enable Floppy Disk Access Detection 0 Keyboard Controller Access (60H or 64H) Detection Control: 0: Disable Keyboard Controller Access Detection 1: Enable Keyboard Controller Access Detection PRELIMINARY Index=44H 46 CY82C693UB Index=43H Default Default ...
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... IRQ11 Monitor Control: 0: Disable IRQ11 Monitoring 1: Enable IRQ11 Monitoring 2 IRQ10 Monitor Control: 0: Disable IRQ10 Monitoring 1: Enable IRQ10 Monitoring 1 IRQ9 Monitor Control: 0: Disable IRQ9 Monitoring 1: Enable IRQ9 Monitoring 0 IRQ8 Monitor Control: 0: Disable IRQ8 Monitoring 1: Enable IRQ8 Monitoring PRELIMINARY 47 CY82C693UB Index=45H Default Index=46H Default ...
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... Enable Hard Disk Access Detection 1 Floppy Disk Access (3f5H) Detection Control: 0: Disable Floppy Disk Access Detection 1: Enable Floppy Disk Access Detection 0 Keyboard Controller Access (60H or 64H) Detection Control: 0: Disable Keyboard Controller Access Detection 1: Enable Keyboard Controller Access Detection PRELIMINARY Index=48H 48 CY82C693UB Index=47H Default Default ...
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... IRQ11 Monitor Control: 0: Disable IRQ11 Monitoring 1: Enable IRQ11 Monitoring 2 IRQ10 Monitor Control: 0: Disable IRQ10 Monitoring 1: Enable IRQ10 Monitoring 1 IRQ9 Monitor Control: 0: Disable IRQ9 Monitoring 1: Enable IRQ9 Monitoring 0 IRQ8 Monitor Control: 0: Disable IRQ8 Monitoring 1: Enable IRQ8 Monitoring PRELIMINARY 49 CY82C693UB Index=49H Default Index=4AH Default ...
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... Enable Hard Disk Access Detection 1 Floppy Disk Access (3f5H) Detection Control: 0: Disable Floppy Disk Access Detection 1: Enable Floppy Disk Access Detection 0 Keyboard Controller Access (60H or 64H) Detection Control: 0: Disable Keyboard Controller Access Detection 1: Enable Keyboard Controller Access Detection PRELIMINARY Index=4CH 50 CY82C693UB Index=4BH Default Default ...
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... IRQ11 Monitor Control: 0: Disable IRQ11 Monitoring 1: Enable IRQ11 Monitoring 2 IRQ10 Monitor Control: 0: Disable IRQ10 Monitoring 1: Enable IRQ10 Monitoring 1 IRQ9 Monitor Control: 0: Disable IRQ9 Monitoring 1: Enable IRQ9 Monitoring 0 IRQ8 Monitor Control: 0: Disable IRQ8 Monitoring 1: Enable IRQ8 Monitoring PRELIMINARY 51 CY82C693UB Index=4DH Default Index=4EH Default ...
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... Mask bits for non-motherboard memory address decode for event detection AD[23:16] Register 54: Programmable I/O Trap 1 Address Range Register #1 (Read/Write) Bit Function 7:0 I/O address AD[7:0] which will automatically generate an SMI. The I/O Trap can be used in conjunction with the I/O restart feature of the Pentium. PRELIMINARY 52 CY82C693UB Index=4FH Default ...
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... Register 5B: Programmable I/O Trap 2 Address Range Register #4 (Read/Write) Bit Function 7:0 Secondary I/O address AD[31:24] which will automatically generate an SMI. The I/O Trap can be used in conjunction with the I/O restart feature of the Pentium. PRELIMINARY 53 CY82C693UB Index=55H Default 00000000 Index=56H Default 00000000 Index=57H ...
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... User Timer 1 Non-motherboard memory access detection control: 0: Disable Non-motherboard memory access detection 1: Enable Non-motherboard memory access detection 0 Throttle Timer Non-motherboard memory access detection control: 0: Disable Non-motherboard memory access detection 1: Enable Non-motherboard memory access detection PRELIMINARY 54 CY82C693UB Index=5CH Default 000 0 0 Index=5DH Default 0 0 ...
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... CY82C693UB Default Index=5FH Default 0000 0000 ...
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... CY82C693UB Index=60H Default 0000 0000 Index=61H Default 0000 00 00 ...
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... Index=63H 57 CY82C693UB Index=62H Default 0000 0000 Default ...
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... Will automatically assert STOPCLK only 11: Will automatically assert STOPCLK 1:0 Hardware Controlled Power Management Control with the expiration of the Suspend Timer: 00: Will not automatically assert STOPCLK 01: Reserved 10: Will automatically assert STOPCLK only 11: Will automatically assert STOPCLK PRELIMINARY Index=64H Index=65H 58 CY82C693UB Default Default ...
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... SMI will remain active after this register is written to one until this register is written to zero. 6 Software SMI Deassertion Control: 0: Normal Operation 1: Force Deassertion of SMI SMI will remain inactive after this register is written to one until this register is written to zero. 5:0 Reserved PRELIMINARY Index=66H Index=67H 59 CY82C693UB Default Default 0 0 000000 ...
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... Will Generate SMI 2 PCI Master Request: 0: Will Not Generate SMI 1: Will Generate SMI 1 Programmable I/O Trap 2 Address Access: 0: Will Not Generate SMI 1: Will Generate SMI 0 Programmable I/O Trap 1 Address Access: 0: Will Not Generate SMI 1: Will Generate SMI PRELIMINARY Index=70H Index=71H 60 CY82C693UB Default Default ...
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... Assertion of INTR (Any Interrupt Request) 0: Will Not Generate SMI 1: Will Generate SMI 1 Assertion of IRQ1 (Interrupt Request 1) 0: Will Not Generate SMI 1: Will Generate SMI 0 Assertion of IRQ0 (Interrupt Request 0) 0: Will Not Generate SMI 1: Will Generate SMI PRELIMINARY Index=72H Index=73H 61 CY82C693UB Default Default ...
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... Assertion of DREQ2 (DMA Request 2) 0: Will Not Generate SMI 1: Will Generate SMI 1 Assertion of DREQ1 (DMA Request 1) 0: Will Not Generate SMI 1: Will Generate SMI 0 Assertion of DREQ0 (DMA Request 0) 0: Will Not Generate SMI 1: Will Generate SMI PRELIMINARY Index=74H Index=75H 62 CY82C693UB Default Default ...
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... SMI was not caused by Floppy Disk Access 1: SMI was caused by Floppy Disk Access WRITE change to register. 1: Clear Register 0 Keyboard Controller Access READ: 0: SMI was not caused by Keyboard Controller Access 1: SMI was caused by Keyboard Controller Access WRITE change to register. 1: Clear Register PRELIMINARY Index=76H 63 CY82C693UB Default ...
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... SMI was caused by a Programmable I/O Trap 2 This Register bit is cleared automatically on a read. 0 Programmable I/O Trap 1 READ: 0: SMI was not caused by a Programmable I/O Trap 1 1: SMI was caused by a Programmable I/O Trap 1 This Register bit is cleared automatically on a read. PRELIMINARY Index=77H 64 CY82C693UB Default ...
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... SMI was not caused by a Software SMI Assertion 1: SMI was caused by a Software SMI Assertion WRITE change to register. 1: Clear Register 0 User Timer 3 Timeout READ: 0: SMI was not caused by a User Timer 3 Timeout 1: SMI was caused by a User Timer 3 Timeout WRITE change to register. 1: Clear Register PRELIMINARY Index=78H 65 CY82C693UB Default ...
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... SMI was not caused by an IRQ1 1: SMI was caused by an IRQ1 WRITE change to register 1: Clear Register 0 Assertion of IRQ0 (Interrupt Request 0) 0: SMI was not caused by an IRQ0 1: SMI was caused by an IRQ0 WRITE change to register 1: Clear Register PRELIMINARY 66 CY82C693UB Index=79H Default ...
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... SMI was not caused by an IRQ9 1: SMI was caused by an IRQ9 WRITE change to register 1: Clear Register 0 Assertion of IRQ8 (Interrupt Request 8) 0: SMI was not caused by an IRQ8 1: SMI was caused by an IRQ8 WRITE change to register 1: Clear Register PRELIMINARY 67 CY82C693UB Index=7AH Default ...
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... SMI was not caused by a DREQ1 1: SMI was caused by a DREQ1 WRITE change to register 1: Clear Register 0 Assertion of DREQ0 (DMA Request 0) 0: SMI was not caused by a DREQ0 1: SMI was caused by a DREQ0 WRITE change to register 1: Clear Register PRELIMINARY 68 CY82C693UB Index=7BH Default ...
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... Register 7C: Reserved Index=7CH Bit Function 7:0 Reserved Register 7D: Reserved Index=7DH Bit Function 7:0 Reserved Register 7E: Reserved Index=7EH Bit Function 7:0 Reserved Register 7F: Reserved Index=7FH Bit Function 7:0 Reserved PRELIMINARY 69 CY82C693UB Default 00000000 Default 00000000 Default 00000000 Default 00000000 ...
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... Disable NMI reporting Sources of NMI can be either from ISA I/O channel error or PCI SERR depending on bits 3 and 2 of register port 61. 6:0 Extended CMOS RAM See CY82C693UB Real-Time Clock Register section. Port 92: PS/2 Reset Control (Read/Write) - I/O Address=092H Bit Function 7:2 Reserved ...
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... Bit Function 7:0 This Read/Write Port can be used for APM software. A write to this register will generate an SMI. Port B3: APM Status Port (Read/Write) - I/O Address=0B3H Bit Function 7:0 This Read/Write Port can be used for APM software. PRELIMINARY 71 CY82C693UB Default 00000000 Default 00000000 ...
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... DMA word count or DMA address registers. The flip-flop is cleared by the asser- tion of the CPURST signal (from the CY82C693UB MAS- TER CLEAR from the DMA registers. The flip-flop can also be programmed by an access to the flip-flop control register. ...
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... Read Low Byte of Current Word Count Register Read High Byte of Current Word Count Register Write Low Byte of Base Word Count Register and Current Word Count Register Write High Byte of Base Word Count Register and Current Word Count Register Read Status Register Write Command Register 73 CY82C693UB ...
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... Terminal Count Not Reached on Channel 1 1: Terminal Count Reached on Channel 1 This bit is cleared by CPURST, Master Clear Status Register Read. 0 Terminal Count Status on Channel 0: 0: Terminal Count Not Reached on Channel 0 1: Terminal Count Reached on Channel 0 This bit is cleared by CPURST, Master Clear Status Register Read. PRELIMINARY 74 CY82C693UB Default ...
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... Function 7:3 Reserved 2 DMA Request Generation Control not generate a DMA Request 1: Force a DMA Request on the channel specified by bits[1:0]. 1:0 DMA Request Channel Selector: 00: Channel 0 01: Channel 1 10: Channel 2 11: Channel 3 PRELIMINARY Undefined Write DMA Request Register 75 CY82C693UB Default Default 00000 0 00 ...
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... Channel 1 10: Channel 2 11: Channel 3 DMA Register 11: DMAC1 DMA Mode Register (Write Only) - I/O Address=00BH I/O Read I/O Write Flip-Flop State Function PRELIMINARY Undefined Write single-bit in DMA Request Mask Register (leaving the rest unchanged) Undefined Write Mode Register 76 CY82C693UB Default 00000 0 00 ...
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... Clear Flip-Flop (Flip-Flop=0). This is a special command. The data lines are ignored. Undefined Perform Master Clear. This is a special command. The data lines are ignored. Undefined Clear DMA Request Mask Bits (Unmask all DMA requests). This is a special command. The data lines are ignored. 77 CY82C693UB Default ...
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... Write High Byte of Base Word Count Register and Current Word Count Register Read Low Byte of Current Address Register Read High Byte of Current Address Register Write Low Byte of Base Address Register and Current Address Register Write High Byte of Base Address Register and Current Address Register 78 CY82C693UB Default 0000 ...
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... Read Low Byte of Current Word Count Register Read High Byte of Current Word Count Register Write Low Byte of Base Word Count Register and Current Word Count Register Write High Byte of Base Word Count Register and Current Word Count Register Read Status Register Write Command Register 79 CY82C693UB ...
Page 80
... Terminal Count Not Reached on Channel 5 1: Terminal Count Reached on Channel 5 This bit is cleared by CPURST, Master Clear Status Register Read. 0 Terminal Count Status on Channel 4: 0: Terminal Count Not Reached on Channel 4 1: Terminal Count Reached on Channel 4 This bit is cleared by CPURST, Master Clear Status Register Read. PRELIMINARY 80 CY82C693UB Default ...
Page 81
... Function 7:3 Reserved 2 DMA Request Generation Control not generate a DMA Request 1: Force a DMA Request on the channel specified by bits[1:0]. 1:0 DMA Request Channel Selector: 00: Channel 4 01: Channel 5 10: Channel 6 11: Channel 7 PRELIMINARY Undefined Write DMA Request Register 81 CY82C693UB Default Default 00000 0 00 ...
Page 82
... Channel 5 10: Channel 6 11: Channel 7 DMA Register 27: DMAC2 DMA Mode Register (Write Only) - I/O Address=0D6H I/O Read I/O Write Flip-Flop State Function PRELIMINARY Undefined Write single-bit in DMA Request Mask Register (leaving the rest unchanged) Undefined Write Mode Register 82 CY82C693UB Default 00000 0 00 ...
Page 83
... Clear Flip-Flop (Flip-Flop=0). This is a special command. The data lines are ignored. Undefined Perform Master Clear. This is a special command. The data lines are ignored. Undefined Clear DMA Request Mask Bits (Unmask all DMA requests). This is a special command. The data lines are ignored. 83 CY82C693UB Default ...
Page 84
... Page Address (Address bits 23-16) for DMAC2 (16-bit DMA Controller), Channel 6 DMA Register 37: DMAC2 Channel 7 Page Address Register (Read/Write) Bit Function 7:0 Page Address (Address bits 23-16) for DMAC2 (16-bit DMA Controller), Channel 7 PRELIMINARY Read DMA Request Mask Register Write DMA Request Mask Register 84 CY82C693UB Default 0000 Index=081H Default 00000000 ...
Page 85
... High Page Address (Address bits 31–24) for DMAC1 (8-bit DMA Controller), Channel 1 DMA Register 43: DMAC1 Channel 0 High Page Address Register (Read/Write) Bit Function 7:0 High Page Address (Address bits 31–24) for DMAC1 (8-bit DMA Controller), Channel 0 PRELIMINARY I/O Address=40BH Undefined Write DMA Request Mask Register 85 CY82C693UB Index=08BH Default 00000000 Default ...
Page 86
... DMA Channel 6 Select: 0: Channel 6 Not Selected 1: Channel 6 Selected 1 DMA Channel 5 Select: 0: Channel 5 Not Selected 1: Channel 5 Selected 0 DMA Channel 4 Select: 0: Channel 4 Not Selected 1: Channel 4 Selected PRELIMINARY Undefined Write DMA Request Mask Register 86 CY82C693UB Index=489H Default 00000000 Index=48AH Default 00000000 Index=48BH Default 00000000 Default ...
Page 87
... CY82C693UB IDE (Bus Mastering) DMA Controller Registers The CY82C693UB supports two channels of DMA for the IDE controller. IDE DMA is compatible with SFF-8038i (the Small Form Factor Committee specification defining bus mastering on IDE). Only 16-bit DMA operation is supported. The IDE DMA controller supports scatter-gather. Scatter-gath- ...
Page 88
... This sets the Base Address (Corresponding to PAD[15:4]) that will be added with an offset value to access the SFF-8038i Registers. 3:2 Reserved, hardwired Reserved 0 Resource Type Indicator (Read Only): This bit is hardwired to ’1’ indicating that the base address field in this register maps to I/O space. PRELIMINARY 88 CY82C693UB Default Default 00000000H 00 ...
Page 89
... Therefore, to find the timeout period, multiply the value in this register by 69.8 ns. Bus Master IDE Test Register (I/O Address 22H with Data = 33 (Index Port); I/O Address 23H is the Data Port) Bit Function 7:0 Undefined on read; Must write 00000000 on writes to this register. PRELIMINARY 89 CY82C693UB Default 00000 0 00 Default 00000 0 ...
Page 90
... The ISR will be reset on an End-of-Interrupt (EOI). An EOI is a special command that the interrupt handler code must issue to the CY82C693UB. A specific EOI can be sent to the CY82C693UB to clear a specific bit in the ISR, or the highest priority interrupt can be cleared (non-specific). Masked inter- rupts will not be cleared for a non-specific EOI. If Automatic ...
Page 91
... Don’t Care 1 Controller Cascade Control: 0: Cascade Mode (for multiple interrupt controllers) 1: Single Mode (There are two controllers in the CY82C693UB. Therefore, this bit should NEVER be programmed to one.) 0 ICW4 Write Status: 0: ICW4 write not required 1: ICW4 write required. ICW2: INTC1 Interrupt Initialization Command Word 2 (Write Only) - I/O Address=021H ...
Page 92
... Automatic End-of-Interrupt (AEOI) Control: 0: Disable AEOI 1: Enable AEOI AEOI should not be enabled if the system supports fully nested interrupts unless this con- troller is a Cascade Master. 0 Microprocessor Mode: 0: Not x86 1: x86 NOTE: This bit must be set to 1. PRELIMINARY 92 CY82C693UB Default Default 000 ...
Page 93
... Don’t Care 1 Controller Cascade Control: 0: Cascade Mode (for multiple interrupt controllers) 1: Single Mode (There are two controllers in the CY82C693UB. Therefore, this bit should NEVER be programmed to one.) 0 ICW4 Write Status: 0: ICW4 write not required 1: ICW4 write required. ICW2: INTC2 Interrupt Initialization Command Word 2 (Write Only) - I/O Address=0A1H ...
Page 94
... IR5 Mask Control: 0: Not Masked 1: Masked 4 IR4 Mask Control: 0: Not Masked 1: Masked 3 IR3 Mask Control: 0: Not Masked 1: Masked 2 IR2 Mask Control: 0: Not Masked 1: Masked 1 IR1 Mask Control: 0: Not Masked 1: Masked 0 IR0 Mask Control: 0: Not Masked 1: Masked PRELIMINARY 94 CY82C693UB Default 000 Default ...
Page 95
... Status Control: 00: Disable Status Read 01: Disable Status Read 10: Contents of the IRR will be read on a status read. 11: Contents of the ISR will be read on a status read. PRELIMINARY 100: Channel 4 101: Channel 5 110: Channel 6 111: Channel 7 95 CY82C693UB Default 000 0 0 000 Default ...
Page 96
... These three bits select which interrupt channel is controlled by the specific commands. 000: Channel 0 (IRQ8) 001: Channel 1 (IRQ9) 010: Channel 2 (IRQ10) 011: Channel 3 (IRQ11) PRELIMINARY 100: Channel 4 (IRQ12) 101: Channel 5 (IRQ13) 110: Channel 6 (IRQ14) 111: Channel 7 (IRQ15) 96 CY82C693UB Default Default 000 0 0 000 ...
Page 97
... The IRR will not change until the read cycle is completed. The PM bit will automatically reset. 1:0 Status Control: 00: Disable Status Read 01: Disable Status Read 10: Contents of the IRR will be read on a status read. 11: Contents of the ISR will be read on a status read. 2CY82C693UB PRELIMINARY 97 CY82C693UB Default ...
Page 98
... CY82C693UB Timer/Counter Registers The CY82C693UB contains a timer/counter which can be used to generate a speaker tone, periodic interrupts, and the ISA refresh. There are three, individually operated, 16-bit counters. The output of counter 0 is internally hardwired to the IRQ0 input of DMA controller 1. The output of counter 1 is tied to the refresh request logic for ISA refresh ...
Page 99
... Hardware triggered strobe 0 Binary/BCD Countdown Status: 0: Binary countdown 1: BCD countdown Timer/Counter Register 2: Counter 1 Register (Read/Write Except for Read-Back Status Command) - Address=041H Bit Function 7:0 Counter 1 Count Value PRELIMINARY Read Only) 99 CY82C693UB Default 00 00 0000 Default 00000000 Default 000 0 Default 00000000 ...
Page 100
... Hardware re-triggerable one-shot X10: Rate Generator (Divide by n counter) X11: Square Wave Output 100: Software triggered strobe 101: Hardware triggered strobe 0 Binary/BCD Countdown Status: 0: Binary countdown 1: BCD countdown PRELIMINARY Read Only) Read Only) 100 CY82C693UB Default 000 0 Default 00000000 Default 000 0 ...
Page 101
... CY82C693UB Real-Time-Clock Registers The RTC inside the CY82C693UB contains a time-of-day clock, an interrupt generating alarm, a 100 year calendar, a software controlled periodic interrupt, and 242 bytes of bat- tery-backable static RAM (for scratch data). An external bat- tery and 32.768-kHz crystal in parallel with a 6-pF capacitor are all that must be provided to enable the RTC to keep time in battery-backed mode ...
Page 102
... PRELIMINARY Index=07H Index=08H Index=09H 30.517 s 61.035 s 122.070 s 244.141 s 488.281 s 976.562 s 1.953125 ms 3.90625 ms 7.8125 ms 15.625 ms 31.25 ms 62.5 ms 125 ms 250 ms 500 ms 102 CY82C693UB Default 00000000 Default 00000000 Default 00000000 Index=0AH Default 0 000 0000 ...
Page 103
... Setting this bit will cause the update cycle to change the time automatically for Daylight Savings Time. The changes take place on the last Sunday in April and the last Sunday in October. This bit is not changed when PSRSTB is asserted. PRELIMINARY Index=0BH 103 CY82C693UB Default ...
Page 104
... NOTE: These Registers are accessed through I/O ports 072H and 073H (not 070H and 071H-the ports for the other RTC registers) Bit Function 7:0 User Defined 3CY82C693UB PRELIMINARY Index=0CH Index=0DH Indices=0EH-7FH Indices=80H-FFH 4CY82C693UB 104 CY82C693UB Default 0000 Default 0 0000000 Default 00000000 Default 00000000 ...
Page 105
... When a key is pressed, a “make” code is sent from the controller in the keyboard to the controller in the CY82C693UB. If the key is not released im- mediately, “make” codes are continually sent to the system. When the key is finally released, a “break” is recognized by the system. Special function keys (such as the < ...
Page 106
... Will send IRQ12 whenever the output buffer is filled with mouse data. 0 Output Buffer Filled with Keyboard Data Interrupt Control: 0: Will not send IRQ1 whenever the output buffer is filled with keyboard data. 1: Will send IRQ1 whenever the output buffer is filled with keyboard data. PRELIMINARY 106 CY82C693UB Default ...
Page 107
... This command will reset bit 4 of the command byte to 0. Keyboard operation will be allowed. C0H Read controller’s input port: This command will cause the controller to read its input port and place the contents into the controller’s output buffer. PRELIMINARY 107 CY82C693UB ...
Page 108
... This command will appear in the output register in response to no password detection initiated by system command A4H. FAH Password installed: This command will appear in the output register in response to a password detection initiated by system command A4H. FEH Resend Command: This command will appear in the output register in response to an illegal command. PRELIMINARY 108 CY82C693UB ...
Page 109
... If the keyboard detects an error in the previous transmission, this command will be sent, requesting the system to send the transmission again. FFH Overrun character (For scan code set 1): When the keyboard exceeds buffer capacity, it places FFH at the bottom of the buffer. When FFH reaches the top of the buffer sent to the system. PRELIMINARY 109 CY82C693UB ...
Page 110
... In Remote Mode, mouse data will only be transmitted in response to a Read Mouse Data command. F2H Read device type: The mouse will return 00H (type ID for mouse) in response to this command. PRELIMINARY 1: Remote Mode 1: Mouse Enabled 1: Scaling 2:1 (Defined by Set Scaling command) 1: Left mouse button pressed 1: Right mouse button pressed. 110 CY82C693UB ...
Page 111
... FAH Acknowledge (ACK) Command: The mouse will acknowledge valid commands by returning the ACK command (except for reset commands). FEH Resend: If the mouse detects an error in the previous transmission, this command will cause the mouse controller to send the transmission again. PRELIMINARY 111 CY82C693UB ...
Page 112
... CY82C693UB PCI Configuration Registers The PCI configuration registers for the CY82C693UB are defined in this section. The registers are accessed by performing configuration read and write cycles (C/BE[3:0]=1010b or 1011b) with the IDSEL signal asserted to the CY82C693UB. PCI to ISA PCI Configuration Registers (Function 0 during Configuration Cycle) ...
Page 113
... Clear Register 13 PCI Master-Abort READ PCI Master-Abort Occurred 1: PCI Master-Abort Occurred WRITE change to register 1: Clear Register 12 CY82C693UB Detection of Target-Abort (from another PCI target) READ PCI Target-Abort Occurred 1: PCI Target-Abort Occurred WRITE change to register 1: Clear Register 11 CY82C693UB Assertion of Target-Abort (CY82C693UB is the target) READ: ...
Page 114
... IRQ11 1100: IRQ12 1101: Reserved 1110: IRQ14 1111: IRQ15 Index=41H with an 8-bit access 1000: Reserved 1001: IRQ9 1010: IRQ10 1011: IRQ11 1100: IRQ12 1101: Reserved 1110: IRQ14 1111: IRQ15 114 CY82C693UB Default 06H Default 80H Default 0 000 0000 Default 0 000 0000 ...
Page 115
... IRQ12 1101: Reserved 1110: IRQ14 1111: IRQ15 Index=43H with an 8-bit access 1000: Reserved 1001: IRQ9 1010: IRQ10 1011: IRQ11 1100: IRQ12 1101: Reserved 1110: IRQ14 1111: IRQ15 Index=44H with an 8-bit access 115 CY82C693UB Default 0 000 0000 Default 0 000 0000 Default ...
Page 116
... Shutdown Cycle Detected WRITE change to register. 1: Clear Register 3:2 Reserved 1 ISA/DMA 0–512K Forwarding: 0: Enable Forwarding 1: Disable Forwarding 0 ISA/DMA 640K–768K Forwarding: 0: Disable Forwarding 1: Enable Forwarding PRELIMINARY Index=45H with an 8-bit access Index=46H with an 8-bit access 116 CY82C693UB Default 000 0 0 Default 000 ...
Page 117
... Internal RTC is in use. 1: External RTC is in use. (Internal RTC is disabled.) 0 External XD Buffer Status (This bit is Read Only): 0: CY82C693UB XD Bus is in use. 1: External buffer is in use to buffer the XD bus. Register 18: ISA/DMA Top of Memory Control (Read/Write) Bit Function 7:4 Top of ISA Memory: ...
Page 118
... Disable AT Refresh 1: Enable AT Refresh 1:0 Keyboard Controller Clock Speed Control PCICLK Speed 25 MHz 00: 6.25 MHz 01: 12.5 MHz 10: 8.33 MHz 11: 16.67 MHz PRELIMINARY Index=49H with an 8-bit access Index=4AH with an 8-bit access 33 MHz 8.25 MHz 16.5 MHz 11 MHz 22 MHz 118 CY82C693UB Default Default ...
Page 119
... IRQ11 1100: IRQ12 1101: Reserved 1110: IRQ14 1111: IRQ15 1000: Reserved 1001: IRQ9 1010: IRQ10 1011: IRQ11 1100: IRQ12 1101: Reserved 1110: IRQ14 1111: IRQ15 119 CY82C693UB Index=4BH with an 8-bit access Default 0 000 0000 Index=4CH with an 8-bit access Default 0 000 0000 ...
Page 120
... This setting is used to allow USB master arbitration to use the SREQ/SGNT signal pair. All other CY82C693UB masters use PREQ/PGNT. Note: This register bit is only for use when the internal PCI arbiter is disabled. If the internal PCI arbiter is used (pin 194 HIGH at power-up), this register bit does not effect CY82C693UB operation. 6:5 ...
Page 121
... Register 24: CY82C693UB USB Control Register 1 (Read/Write) - Index=4EH with an 8-bit access Bit Function 7:6 USB Host Controller Test Mode Selection 5 USB Host Controller Test Mode Enable 4 USB Host Controller IRQ1 Enable: 0: Disabled 1: Enabled 3 USB Host Controller IRQ12 Enable: 0: Disabled 1: Enabled This bit is write-only. Undefined on read. ...
Page 122
... PCI Configuration Registers (Function 1 during Configuration Cycle) Register 0: Vendor ID Number (Read Only) Bit Function 15:0 Cypress ID Number: 0001000010000000 Register 1: Device ID Number (Read Only) Bit Function 15:0 CY82C693UB Device ID Number: 1100011010010011 Register 2: Command Register (Read/Write) Bit Function 15:10 Reserved. 9 Reserved, Must be set SERR Reporting Enable: ...
Page 123
... This bit is not used by the IDE controllers. 13 PCI Master-Abort READ PCI Master-Abort Occurred 1: PCI Master-Abort Occurred WRITE change to register 1: Clear Register 12 CY82C693UB Detection of Target-Abort (from another PCI target) READ PCI Target-Abort Occurred 1: PCI Target-Abort Occurred WRITE change to register 1: Clear Register 11 CY82C693UB Assertion of Target-Abort (CY82C693UB is the target) READ: ...
Page 124
... The Primary IDE Channel Interrupt is connected to PCI INTA internally. Note: Register Indices 3EH-3FH will return all zeroes when read. PRELIMINARY Index=14H with a 32-bit access Index=3DH with an 8-bit access 124 CY82C693UB Default 00000000H Index=20H with a 32-bit access Default 00000000H Index=3CH with an 8-bit access ...
Page 125
... The value programmed into this register +1 will be the duration (in AT Clock cycles) of the asserted IOR signal. 3:0 16-Bit Master Drive IDE IOR Command Recovery Time: The value programmed into this register +1 will be the duration (in AT Clock cycles) that IOR must be deasserted between transfers. PRELIMINARY Index=40H with a 32-bit access 125 CY82C693UB Default 00000000000 000 ...
Page 126
... Note: The 8-bit IDE Command Registers are used for mode 0, 1, and 2 drives. For mode 3 and 4 drives, the 8 and 16 bit timings are the same. PRELIMINARY 126 CY82C693UB Index=4DH with an 8-bit access Default 0110 1110 Index=4EH with an 8-bit access ...
Page 127
... IORDY during read transactions. 1:0 Write Synchronization Control: The value in this register selects the number of PCI clocks used to synchronize the rising edge of IORDY during write transactions. PRELIMINARY 127 CY82C693UB Index=52H with an 8-bit access Default 0000 01 01 Index=53H with an 8-bit access ...
Page 128
... PCI Configuration Registers (Function 2 during Configuration Cycle) Register 0: Vendor ID Number (Read Only) Bit Function 15:0 Cypress ID Number: 0001000010000000 Register 1: Device ID Number (Read Only) Bit Function 15:0 CY82C693UB Device ID Number: 1100011010010011 Register 2: Command Register (Read/Write) Bit Function 15:10 Reserved. 9 Reserved, must be set SERR Reporting Enable: ...
Page 129
... This bit is not used by the IDE controllers. 13 PCI Master-Abort READ PCI Master-Abort Occurred 1: PCI Master-Abort Occurred WRITE change to register 1: Clear Register 12 CY82C693UB Detection of Target-Abort (from another PCI target) READ PCI Target-Abort Occurred 1: PCI Target-Abort Occurred WRITE change to register 1: Clear Register 11 CY82C693UB Assertion of Target-Abort (CY82C693UB is the target) READ: ...
Page 130
... IDE read state machine will attempt to the IDE drive when the AT bus grant is received. Note: Register Indices 44H-47H will return all zeroes when read. PRELIMINARY Index=14H with a 32-bit access Index=40H with a 32-bit access 130 CY82C693UB Default 00000000H Index=3CH with an 8-bit access Default 15H ...
Page 131
... Slave Drive IDE IOW Command Recovery Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW must be deasserted between transfers. PRELIMINARY 131 CY82C693UB Index=48H with a 32-bit access Default 000000H 0011 0011 Index=4CH with an 8-bit access ...
Page 132
... IORDY during read transactions. 1:0 Write Synchronization Control: The value in this register selects the number of PCI clocks used to synchronize the rising edge of IORDY during write transactions. PRELIMINARY 132 CY82C693UB Index=50H with an 8-bit access Default 1010 1010 Index=51H with an 8-bit access Default ...
Page 133
... The USB Host Controller always generates fast back-to-back access. Therefore, this bit must be set SERR Reporting Enable: 0: Disabled 1: Enabled 7 Wait Cycle Control. Always 0. 6 PERR Detection Enabled. Not supported by CY82C693UB. 5 VGA Palette Snooping. Always 0 4 Memory Write and Invalidate Command Enable 3 Special Cycle Enable. Always 0. 2 PCI Master Enable: 0: Bus Master Disabled ...
Page 134
... Clear register 10:9 DEVSEL Timing Status: These register bits are Read Only and will always read as 01 (medium timing) 8 Data Parity Reported. Not supported by CY82C693UB (PERR) 7 Fast Back-to-Back Transfer Capable. This Read Only bit will always return 1 6:0 Reserved. Always 0. Register 4: Revision ID Number (Read Only) - Index=08H with an 8-bit access ...
Page 135
... Interrupt Line. This register identifies which of the system interrupt controllers the device’s interrupt pin is connected to. The value of this register is used by the device drivers and has no direct meaning to the USB Host Controller. PRELIMINARY 135 CY82C693UB Default 0C0310H Default 00H Default ...
Page 136
... Register 16: ASIC Operational Mode Enable Register (Read/Write) - Index=44H with an 8-bit access Bit Function 7:0 ASIC Operational Mode Enable. For normal USB Host Controller operation this register must remain as 0. PRELIMINARY 136 CY82C693UB Default 01H Default 00H Default 00H Default 0XXXXXXXH ...
Page 137
... Specifies the number of Control Endpoints serviced for every Bulk Endpoint. Encoding where N is the number of Control Endpoints (i.e., ‘00’ Control Endpoint; ‘11’ Control Endpoints). PRELIMINARY Address Register in the USB Host Controller PCI Configura- tion Registers) and the offset value of the register. 137 CY82C693UB Default 000000H 10H Default 0H 0 ...
Page 138
... This bit is set when the Frame Management block signals a ‘Start of Frame’ event. 1 Writeback Done Head: This bit is set after the Host Controller has written HcDoneHead to HccaDoneHead. 0 Scheduling Overrun: This bit is set when the List Processor determines a Schedule Overrun has occurred. PRELIMINARY 138 CY82C693UB Default Default ...
Page 139
... Enable interrupt generation due to Resume Detected 2 Start Of Frame Enable: 0: Ignore 1: Enable interrupt generation due to Start of Frame 1 Writeback Done Head Enable: 0: Ignore 1: Enable interrupt generation due to Writeback Done Head 0 Scheduling Overrun Enable: 0: Ignore 1: Enable interrupt generation due to Scheduling Overrun PRELIMINARY 139 CY82C693UB Default ...
Page 140
... Register 7: HcPeriodCurrentED (Read/Write) - Offset=1CH with a 32-bit access Bit Function 31:4 Period Current ED: Pointer to the current Periodic List ED. 3:0 Reserved. Register 8: HcControlHeadED (Read/Write) - Offset=20H with a 32-bit access Bit Function 31:4 Control Head ED: Pointer to the Control List Head ED. 3:0 Reserved. PRELIMINARY 140 CY82C693UB Default Default 0H 0H Default 0H 0H ...
Page 141
... USBOperational state the counter decrements each 12 MHz clock period. When the count reaches 0, the end of a frame has been reached. The counter reloads with FrameInter- val at that time. In addition, the counter loads when the Host Controller transitions into USB- Operational state. PRELIMINARY 141 CY82C693UB Default 0H 0H Default 0H ...
Page 142
... Individual Over-Current This bit is only valid when NoOverCurrentProtection is cleared. This bit should be written ‘0’. 10 Device Type: Read Only. The CY82C693UB USB Host Controller is not a compound device Power Switching: The Host Controller implements a global power switching mode. 0: Ports are power switched ...
Page 143
... Port 1 2: Port 2 ... 15: Port 15 Unimplemented ports are reserved, read/write ‘0’. Note: THis register is only reset by power-on reset (PCIRST written during system initialization to configure the Root Hub. These bits should not be written during normal configuration. PRELIMINARY 143 CY82C693UB Default 0000H 0000H ...
Page 144
... No over-current condition 1: Over-current condition 0 READ: Local Power Status. Not supported. Always read ‘0’. WRITE: Clear Global Power. Writing a ‘1’ issues a ClearGlobalPower command to the ports. Writing a ‘0’ has no effect. Note: This register is reset by the USBReset state. PRELIMINARY 144 CY82C693UB Default ...
Page 145
... OVRCUR pin dedicated to this port. This field is only valid if NoOverCurrentProtection is cleared and OverCurrentProtectionMode is set over-current condition 1: Over-current condition WRITE: Clear Port Suspend. Writing a ‘1’ initiates the selective resume sequence for the port. Writing a ‘0’ has no effect. PRELIMINARY 145 CY82C693UB Default ...
Page 146
... I/O registers 60H and 64H and generate IRQ1 and/or IRQ12 when appropriate. Additionally, the Host Controller will generate an emulation interrupt at appropri- ate times to invoke the emulation software. Note: This register is used to enable and control the legacy keyboard and mouse emulation hardware and report various status information. PRELIMINARY 146 CY82C693UB Default Default 0H ...
Page 147
... AuxOutputFull is set to ‘1’ then an IRQ12 will be generated as long as this bit is set to ‘1’. While this bit is ‘0’ and CharacterPending in HceControl is set to ‘1’, an emulation interrupt condition exists. Note: This register is the emulation side of the legacy Status register. PRELIMINARY 147 CY82C693UB Default 0H - Default 0H ...
Page 148
... Input Leakage Current IL I Output Leakage OL C Input Capacitance IN C Output Capacitance OUT I Power Supply Current CC PRELIMINARY Operating Range Range Commercial 125 C Extended Temp 0. Description 66 MHz 148 CY82C693UB Ambient Temperature DDQ + 3. 3.3V 0.3V Min. Max. Unit 4.5 5 0.5 0 ...
Page 149
... VALIDI SA PAD[31:0] ADDRESS MEMORY PC/BE[31:0] VALID BYTEENABLES READ DEVSEL IRDY TRDY ATCLK BALE LA[17:23] SA[19:0]SBHE MRD OR IOR SD[15:0] IOCHRDY (STANDARD OR 0WS) IOCHRDY (WAIT STATES) 0WS (STANDARD OR WAIT STATES) 0WS (0WS) PRELIMINARY SUBTRACTIVE DECODE 149 CY82C693UB CLK EDGE A VALID ADDRESS VALID ADDRESS ...
Page 150
... CLK EDGE A PCICLK FRAME PAD[31:0] PC/BE[31:0] VALID BYTE ENABLES DEVSEL IRDY TRDY ATCLK BALE VALID LA[17:23] ADDRESS VALID SA[19:0]SBHE ADDRESS MRD OR IOR SD[15:0] IOCHRDY (STANDARD OR 0WS) IOCHRDY (WAIT STATES) 0WS (STANDARD OR WAIT STATES) 0WS (0WS) PRELIMINARY VALID DATA VALID DATA 150 CY82C693UB ...
Page 151
... Switching Waveforms (continued) PCI Write to ISA Post Write Buffer (Subtractive Decode Set to 6 CLKS) FRAME ISA PAD[31:0] ADDRESS MEM WRITE OR IO PC/BE[31:0] WRITE DEVSEL IRDY TRDY PRELIMINARY VALID BYTE ENABLES 151 CY82C693UB VALID DATA ...
Page 152
... DMA/Master Operation (Memory Read/IO Write) ATCLK DRQX DACKX AEN, BALE LA[17:23] SA[19:0] SBHE IOCHRDY MRD IOW SD[15:0] PCICLK FREQACK 693 691 GNTBSY FRAME PAD[31:0] PC/BE[3:0] IRDY TRDY PRELIMINARY VALID MEMORY ADDRESS MEM DATA ADDR MEM BYTE ENABLES RD 152 CY82C693UB VALID DATA ...
Page 153
... DMA/Master Operation (IO Read/Memory Write) ATCLK DRQX DACKX AEN, BALE LA[17:23] SA[19:0] SBHE IOCHRDY MWT IOR SD[15:0] PCICLK FREQACK 693 691 GNTBSY FRAME PAD[31:0] PC/BE[3:0] IRDY TRDY PRELIMINARY VALID MEMORY ADDRESS ADDR MEM WR 153 CY82C693UB VALID DATA VALID DATA BYTE ENABLES ...
Page 154
... Switching Waveforms (continued) Reset OSC PWGD PCIRST COLD RESET CPURST PCICLK INIT (WARM RESET) PRELIMINARY IMS TRESETD TRESETSU 154 CY82C693UB TWRESETDR TWRESETDF ...
Page 155
... Switching Waveforms (continued) Power Management (Hardware Controlled) ATCLK PCICLK STOPCLK Power Management (Software Controlled) CPUCLK SMI t SMISU PRELIMINARY t SMEH 155 CY82C693UB STOP CLK STOP CLK THROTTLE THROTTLE LOW TIME HIGH TIME t SMEH t SMIH ...
Page 156
... READ PCIIDE(15:0) WRITE PCIIDE(15:0) *Preface all of these indices with SWIPEDMA (e.g. TH becomes SWPIDEDMA PRELIMINARY PIDE t0 VALID IDE ADDRESS PIDE t2 PIDE t1 PIDE t2 PIDE t7 PIDE tA PIDE tRD PIDE tB t0* tI* tD* tE* tS* tG 156 CY82C693UB PIDE t9 PIDE t8 PIDE t2i PIDE t4 PIDE t5 t6 PIDE t6Z tJ* tF* tH* ...
Page 157
... Switching Waveforms (continued) Multiword DMA Transfer DMARQ DMACK tI* IDEIOR/IDEIOW READ PCIIDE(15:0) tGr* WRITE PCIIDE(15:0) tGw* PRELIMINARY t0* tD* tK* tE* tF* tH* 157 CY82C693UB tL* tJ* tZ* ...
Page 158
... Switching Waveforms (continued) AT Refresh Timing ATCLK REFSH MEMR SMEMR XA [10:0] Interrupt Acknowledge Cycle PCICLK FRAME PAD[31:0] INTERRUPT PC/BE[3:0] ACKNOWLEDGE IRDY TRDY PRELIMINARY T120 T119 ROW ADDRESS LOW ORDER BYTE ENABLED 158 CY82C693UB T118 INTERRUPT VECTOR ...
Page 159
... Switching Waveforms (continued) CY82C693 Configuration Access PCICLK FRAME PAD[31:0] CONFIG ADDRESS IDSEL PIN OF 693 CONFIG PC/BE[3: IRDY TRDY DEVSEL PRELIMINARY CONFIG DATA VALID BYTEENABLES 159 CY82C693UB ...
Page 160
... Switching Waveforms (continued) 693 Generated Retry (For Accesses Requiring More Than 16 PCI Clock Cycles to Complete) PCICLK FRAME 693 PAD[31:0] ADDRESS PC/BE[3: IRDY TRDY STOP DEVSEL PRELIMINARY 16 PCI CLOCK CYCLES VALID BYTE ENABLES 160 CY82C693UB RETRY CYCLE 693 ADDRESS ...
Page 161
... Switching Waveforms (continued) 693 PCI Disconnect on a NON Burst Cycle (If Initiator does not Deassert Frame) PCICLK FRAME 693 PAD[31:0] ADDRESS PC/BE[3: IRDY TRDY STOP DEVSEL PRELIMINARY VALID BYTE ENABLES 161 CY82C693UB VALID DATA ...
Page 162
... ISA Master Memory Pre-Read PCICLK FRAME IRDY DEVSEL TRDY A BE0 C/BE 1WS BURST WRITE WITH FASTEST TARGET PRELIMINARY BE0 BE1 BE1 0 WS BURST WRITE WITH FASTEST TARGET 162 CY82C693UB A BE0 BE1 C BE0 STOP 0WS BURST WRITE DISCONNECT & RETRY WITH FASTEST TARGET 82C693UB–4 ...
Page 163
... PCI Master Subtractive Decode “DEVSEL” Timing 5 PCICLK FRAME IRDY DEVSEL TRDY/ STOP (SUB DECODE=4PCICLK) Ordering Information Ordering Code Package Name CY82C693UB-NC N208 CG4973AT N208 Document #: 38-00684 PRELIMINARY PCI Master Subtractive Decode “DEVSEL” Timing PCICLK FRAME IRDY DEVSEL TRDY/ STOP 82C693UB– ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY 208-Lead Plastic Quad Flatpack N208 CY82C693UB ...