CY7C026A-15AI Cypress Semiconductor Corporation., CY7C026A-15AI Datasheet
CY7C026A-15AI
Specifications of CY7C026A-15AI
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CY7C026A-15AI Summary of contents
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... CY7C026A CY7C036A16K x 16/18 Dual-Port Static RAM Features • True dual-ported memory cells that allow simultaneous access of the same memory location • 16K x 16 organization (CY7C026A) • 16K x 18 organization (CY7C036A) • 0.35-micron CMOS for optimum speed/power [1] • High-speed access: 12 /15/20 ns • Low operating power — ...
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... I/O 5 10L I/O 6 11L I/O 7 12L I/O 8 13L GND 9 I/O 10 14L I/O 11 15L VCC 12 GND VCC Document #: 38-06046 Rev. *C 100-Pin TQFP (Top View CY7C026A (16K x 16 CY7C026A CY7C036A INT L 64 BUSY L 63 GND 62 M/S 61 BUSY R 60 INT ...
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... SB3 Document #: 38-06046 Rev. *C 100-Pin TQFP Top View CY7C036A (16K x 18 CY7C026A CY7C036A [1] -12 12 195 55 0.05 CY7C026A CY7C036A 13L INT 65 L BUSY 64 L GND 63 M/S 62 BUSY 61 R INT 13R CY7C026A CY7C026A CY7C036A CY7C036A -15 -20 Unit 190 180 0.05 0.05 mA Page [+] Feedback ...
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... CC GND NC Architecture The CY7C026A and CY7C036A consist of an array of 16K words of 16 and 18 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port ...
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... The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C026A and CY7C036A provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within t of each other, the busy logic will determine which PS port has access ...
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... Indust. 135 Com’l. 0.05 0.5 0.05 Indust. 0.05 Com’l. 115 185 110 Indust. 125 Test Conditions ° MHz 5.0V CC CY7C026A CY7C036A Ambient Temperature V CC ° ° 5V ± 10 +70 C ° ° 5V ± 10% – +85 C -20 Max. Min. Typ. Max. Unit 2 ...
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... TH OUTPUT 1.4V TH (b) Thévenin Equivalent (Load 1) [9] 3.0V 10% GND ≤ Capacitance (pF) (b) Load Derating Curve CY7C026A CY7C036A 893Ω OUTPUT 347Ω (c) Three-State Delay (Load 2) (Used for & HZWE LZWE including scope and jig) ALL INPUT PULSES 90% 90% 10% ≤ ...
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... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 16. For 15 ns industrial parts t Min. is 0.5 ns. HD Document #: 38-06046 Rev. *C [10] CY7C026A CY7C036A [1] -12 -15 Min. Max. Min. Max less than t and t is less than t . HZCE LZCE HZOE LZOE CY7C026A CY7C036A -20 Min. Max. Unit time. SCE Page [+] Feedback ...
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... SEM Address Access Time SAA Data Retention Mode The CY7C026A and CY7C036A are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, ...
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... To access RAM SEM = Document #: 38-06046 Rev. *C [20, 21, 22 DATA VALID [20, 23, 24] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE . This waveform cannot be used for semaphore reads access semaphore SEM = CY7C026A CY7C036A t OHA t HZCE t HZOE DATA VALID OHA t HZCE t HZCE . Page [+] Feedback ...
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... If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document #: 38-06046 Rev. *C [25, 26, 27, 28 [28] t PWE [31] t HZWE t SD [25, 26, 27, 33 SCE LOW CE or SEM and a LOW PWE . CY7C026A CY7C036A [31] t HZOE LZWE NOTE allow the I/O drivers to turn off and data HZWE SD Page [+] Feedback ...
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... SPS Document #: 38-06046 Rev. *C [34] t SAA VALID ADRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE [35, 36, 37] MATCH t SPS MATCH = CE = HIGH CY7C026A CY7C036A t OHA t ACE DATA VALID OUT t DOE Page [+] Feedback ...
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... Timing Diagram of Read with BUSY (M/S = HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S = LOW) R/W BUSY Note: 38 LOW Document #: 38-06046 Rev. *C [38 MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C026A CY7C036A BHA t BDD t DDD VALID Page [+] Feedback ...
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... BUSY will be asserted. PS Document #: 38-06046 Rev. *C [39] ADDRESS MATCH BLC ADDRESS MATCH BLC [39 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C026A CY7C036A t BHC t BHC Page [+] Feedback ...
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... INT L Notes: 40. t depends on which enable pin ( depends on which enable pin (CE INS INR L Document #: 38-06046 Rev WRITE 3FFF [40 [41] t INR t WC WRITE 3FFE [40 [41] t INR ) is deasserted first R asserted last. L CY7C026A CY7C036A t RC READ 3FFF t RC READ 3FFE Page [+] Feedback ...
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... Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C026A CY7C036A –I/O Operation 8 Deselected: Power-Down Deselected: Power-Down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only ...
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... Ordering Information 16K x16 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C026A-12AC 15 CY7C026A-15AC CY7C026A-15AXC CY7C026A-15AI 20 CY7C026A-20AC CY7C026A-20AXC Speed (ns) Ordering Code [1] 12 CY7C036A-12AC 15 CY7C036A-15AC CY7C036A-15AI 20 CY7C036A-20AC Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 All products and company names mentioned in this document may be the trademarks of their respective holders ...
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... Document History Page Document Title: CY7C026A/CY7C036A 16K X 16/18 Dual-Port Static RAM Document Number: 38-06046 Issue REV. ECN NO. Date ** 110198 09/29/01 *A 122296 12/27/02 *B 237621 SEE ECN *C 393454 See ECN Document #: 38-06046 Rev. *C Orig. of Change Description of Change SZV Change from Spec number: 38-00832 to 38-06046 ...