CY7C09369A-6AC Cypress Semiconductor Corporation., CY7C09369A-6AC Datasheet

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CY7C09369A-6AC

Manufacturer Part Number
CY7C09369A-6AC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY7C09369A-6AC

Case
QFP-100L
25/0251
Cypress Semiconductor Corporation
Document #: 38-06050 Rev. *A
Features
Notes:
Logic Block Diagram
1.
2.
3.
• True dual-ported memory cells which allow simulta-
• Two Flow-Through/Pipelined devices
• Three Modes
• Pipelined output mode on both ports allows fast 100-
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5
R/W
UB
CE
CE
LB
OE
FT/Pipe
I/O
I/O
A
CLK
ADS
CNTEN
CNTRST
neous access of the same memory location
MHz cycle time
— 16K x 16/18 organization (CY7C09269A/369A)
— Flow-Through
— Pipelined
— Burst
0L
See page 6 for Load Conditions.
I/O
I/O
L
8/9L
0L
L
0L
1L
L
–A
8
0
L
L
L
–I/O
–I/O
–I/O
13L
–I/O
L
L
15
7
L
7/8L
for x16 devices. I/O
[2]
[3]
for x16 devices; I/O
15/17L
14
For the most recent information, visit the Cypress web site at www.cypress.com
8/9
8/9
0
9
–I/O
0/1
–I/O
0/1
1
0
1b
Counter/
Register
Address
Decode
8
17
b
for x18 devices.
0b 1a 0a
for x18 devices.
a
[1]
/7.5/9/12 ns (max.)
3901 North First Street
Control
I/O
True Dual-Ported
RAM Array
• Low operating power
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
• Dual Chip Enables for easy depth expansion
• Upper and Lower Byte Controls for Bus Matching
• Automatic power-down
• Commercial temperature range
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to
IDT709269
— Active = 195 mA (typical)
— Standby = 0.05 mA (typical)
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
Control
I/O
16K x16/18 Synchronous
San Jose
Dual Port Static RAM
0a
a
1a
Counter/
Register
Address
Decode
0b
b
CA 95134
1b
0/1
1
0
0/1
Revised December 27, 2002
8/9
8/9
CY7C09269A
CY7C09369A
14
I/O
8/9R
408-943-2600
I/O
0R
CNTRST
–I/O
A
FT/Pipe
CNTEN
0R
–I/O
–A
ADS
15/17R
R/W
CLK
CE
CE
OE
UB
LB
[2]
[3]
7/8R
13R
0R
1R
R
R
R
R
R
R
R
R
R
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Related parts for CY7C09369A-6AC

CY7C09369A-6AC Summary of contents

Page 1

... IDT709269 I/O Control Control Counter/ Address True Dual-Ported Register RAM Array Decode for x18 devices. 17 for x18 devices. 8 • 3901 North First Street CY7C09269A CY7C09369A 16K x16/18 Synchronous Dual Port Static RAM 0/1 8/9 I/O 8/9R I/O 8/9 14 Counter/ Address ...

Page 2

... Functional Description The CY7C09269A and CY7C09369A are high-speed synchro- nous CMOS 16K, 32K, and 64K x 16/18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. isters on control, address, and data lines allow for minimal set- up and hold times ...

Page 3

... Typical Operating Current I (mA) CC Typical Standby Current for I (mA) SB1 (Both Ports TTL Level) Typical Standby Current for I (mA) SB3 (Both Ports CMOS Level) Document #: 38-06050 Rev. *A 100-Pin TQFP (Top View CY7C09369A (16K x 18 CY7C09269A CY7C09269A CY7C09369A CY7C09369A [ 100 83 6.5 7.5 250 ...

Page 4

... For read operations both Input Voltage ............................................–0.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >1100V Latch-Up Current..................................................... >200 mA Operating Range Range Commercial CY7C09269A CY7C09369A AND CE must be asserted MAX –I/O ). 8/9L 15/17L Ambient Temperature ...

Page 5

... Test Conditions MHz 5.0V CC AND CE must be asserted to their active states ( CY7C09269A CY7C09369A -9 -12 Unit 2.4 V 0.4 0.4 V 2.2 V 0.8 0 – 215 360 195 300 145 205 ...

Page 6

... Document #: 38-06050 Rev 250 TH OUTPUT 1.4V TH (b) Thévenin Equivalent (Load 1) [8] 3.0V 10% GND Capacitance (pF) (b) Load Derating Curve CY7C09269A CY7C09369A 893 OUTPUT 347 (c) Three-State Delay (Load 2) (Used for & t CKLZ OLZ OHZ including scope and jig) ALL INPUT PULSES 90% 90% 10 Page ...

Page 7

... Test conditions used are Load 2. 10. This parameter is guaranteed by design, but it is not production tested. Document #: 38-06050 Rev. *A CY7C09269A CY7C09369A [ Min. Max. Min. Max. Min. Max 100 6.5 7.5 12 6 6.5 7 CY7C09269A CY7C09369A -12 Min. Max. Unit 33 MHz 50 MHz Page [+] Feedback ...

Page 8

... Q n n+1 t OHZ [11, 12, 13, 14 CL2 A A n+1 n+2 t CD2 CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09269A CY7C09369A n+3 t CKHZ Q n OLZ n n+1 n+2 t OHZ ...

Page 9

... CD2 HC CD2 SC CKHZ CKLZ [17, 18, 19, 20] NO MATCH t CD1 NO MATCH t CWDD VALID . for the left port, which is being written to. IH CY7C09269A CY7C09369A CD2 CKHZ CKLZ CD2 CKHZ CD2 CKLZ t CD1 VALID >maximum specified, then data is not valid CWDD CCS Page [+] Feedback ...

Page 10

... During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document #: 38-06050 Rev. *A [14, 21, 22, 23 n+1 n CD2 CKHZ OPERATION [14, 21, 22, 23 n+1 n+2 n n+2 n+3 t CD2 OHZ WRITE . IH CY7C09269A CY7C09369A A A n+3 n CD2 CKLZ Q n+3 WRITE READ A A n+4 n CKLZ CD2 Q n+4 READ Page [+] Feedback ...

Page 11

... DATA OUT OE Document #: 38-06050 Rev. *A [12, 14, 21, 22 n+1 n+2 n n+2 t CD1 Q n+1 t CKHZ NO READ OPERATION [12, 14, 21, 22 n+1 n+2 n n+2 n OHZ READ WRITE CY7C09269A CY7C09369A n+3 n CD1 CD1 Q n CKLZ WRITE READ A A n+4 n CD1 t CD1 Q n CKLZ DC READ Page [+] Feedback ...

Page 12

... Document #: 38-06050 Rev. *A [24 SAD t t SCN t CD2 n+1 COUNTER HOLD READ WITH COUNTER [24 n+1 n+2 READ WITH COUNTER . IH CY7C09269A CY7C09369A HAD HCN Q Q n+2 n+3 READ WITH COUNTER t t SAD HAD t t SCN HCN Q n+3 READ COUNTER HOLD WITH COUNTER Page [+] Feedback ...

Page 13

... The “Internal Address” is equal to the “External Address” when ADS = V Document #: 38-06050 Rev. *A [25, 26 n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and equals the counter output when ADS = V IL CY7C09269A CY7C09369A n+2 n+3 n n+3 n+4 WRITE WITH COUNTER . IH Page [+] Feedback ...

Page 14

... SD DATA DATA OUT COUNTER RESET Notes: 27 UB, and 28. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06050 Rev WRITE READ ADDRESS 0 ADDRESS 0 ADDRESS 1 CY7C09269A CY7C09369A n n READ READ ADDRESS n Page [+] Feedback ...

Page 15

... CNTRST I/O Mode Reset out( Load out( Hold out( Increment out(n+ CY7C09269A CY7C09369A Operation [32] Deselected [32] Deselected Write [34] Read Outputs Disabled Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation Page [+] Feedback ...

Page 16

... CY7C09269A-9AC 12 CY7C09269A-12AC 16K x18 Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09369A-6AC 7.5 CY7C09369A-7AC 9 CY7C09369A-9AC 12 CY7C09369A-12AC Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06050 Rev. *A © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...

Page 17

... Document Title: CY7C09269A/CY7C09369A 16K x 16/18 Synchronous Dual Port Static RAM Document Number: 38-06050 Issue Orig. of REV. ECN NO. Date Change ** 110202 11/11/01 *A 122300 12/27/02 Document #: 38-06050 Rev. *A Description of Change SZV Change from Spec number: 38-00836 to 38-06050 RBI Power up requirements added to Maximum Ratings Information ...

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