CY7C1069AV33-10ZC Cypress Semiconductor Corporation., CY7C1069AV33-10ZC Datasheet

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CY7C1069AV33-10ZC

Manufacturer Part Number
CY7C1069AV33-10ZC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1069AV33-10ZC
Manufacturer:
CYPRESS
Quantity:
26
Part Number:
CY7C1069AV33-10ZC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Cypress Semiconductor Corporation
Document #: 38-05255 Rev. *F
Features
CE
CE
• High speed
• Low active power
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
• Available in Pb-free and non Pb-free 54-pin TSOP II ,
Logic Block Diagram
— t
— 990 mW (max.)
non Pb-free 60-ball fine-pitch ball grid array (FBGA)
package
1
2
AA
= 10, 12 ns
WE
OE
A
A
A
A
A
A
A
A
A
A
A
A
A
11
12
10
0
1
2
3
4
5
9
6
7
8
Data in Drivers
2048K x 8
1
DECODER
ARRAY
COLUMN
and CE
2
198 Champion Court
features
POWER
DOWN
Functional Description
The CY7C1069AV33 is a high-performance CMOS Static
RAM organized as 2,097,152 words by 8 bits. Writing to the
device is accomplished by enabling the chip (by taking CE
LOW and CE
Reading from the device is accomplished by enabling the chip
(CE
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
See the truth table at the back of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH or CE
during a Write operation (CE
LOW).
The CY7C1069AV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
60-ball fine-pitch ball grid array (FBGA) package.
1
LOW and CE
San Jose
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
LOW), the outputs are disabled (OE HIGH), or
HIGH) and Write Enable (WE) inputs LOW.
0
1
2
3
4
5
6
7
,
2
CA 95134-1709
HIGH) as well as forcing the Output
2M x 8 Static RAM
Pin Configurations
0
through I/O
1
I/O
I/O
CE
V
CE
V
I/O
NC
V
V
I/O
NC
WE
A
A
V
A
A
A
NC
NC
NC
CC
Revised August 3, 2006
CC
LOW, CE
SS
A
A
A
A
CC
A
SS
19
18
17
16
15
6
7
4
3
2
1
0
1
2
0
1
CY7C1069AV33
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
1
2
3
4
5
6
7
8
9
10
11
12
Top View
TSOP II
7
) are placed in a
2
53
50
39
38
37
36
35
33
32
54
52
51
49
48
47
46
45
43
42
40
34
31
30
29
28
HIGH, and WE
44
41
408-943-2600
NC
V
I/O
V
A
V
DNU
A
V
NC
V
NC
I/O
A
A
A
A
NC
OE
A
A
A
A
I/O
NC
A
I/O
SS
SS
CC
5
6
7
8
9
SS
10
11
12
13
14
CC
20
[1, 2]
5
4
3
2
1
1
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Related parts for CY7C1069AV33-10ZC

CY7C1069AV33-10ZC Summary of contents

Page 1

... HIGH or CE LOW), the outputs are disabled (OE HIGH during a Write operation (CE LOW). The CY7C1069AV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and a 60-ball fine-pitch ball grid array (FBGA) package. I/O 0 I/O 1 I/O ...

Page 2

... NC pins are not connected on the die. 2. DNU pins have to be left floating or tied to VSS to ensure proper application. Document #: 38-05255 Rev. *F –10 10 275 50 60-ball FBGA (Top View CE2 CE1 I I I/O 2 I DNU CY7C1069AV33 –12 Unit 12 ns 260 Page [+] Feedback ...

Page 3

... Test Conditions T = 25° MHz 3. [ components of the test environment All input pulses 90% 10% (c) to the data retention (V DD CY7C1069AV33 [3] ................................ –0. 0.5V CC Ambient Temperature V CC 3.3V ± 0.3V 0°C to +70°C –40°C to +85°C –10 –12 Max. Min. Max. Unit 2 ...

Page 4

... DATA RETENTION MODE 3.0V V > CDR to the data retention (V DD time has to be provided initially before a Read/Write operation is power are specified with a load capacitance ( Test Loads. Transition is measured ±200 mV from , and WE LOW LOW/CE HIGH 1 2 and t HZWE CY7C1069AV33 –12 Max. Min. Max. Unit ...

Page 5

... DATA OUT t LZSCE SUPPLY CURRENT Notes: 13. Device is continuously selected 14 HIGH for Read cycle. 15. Address valid prior to or coincident with CE transition LOW and CE 1 Document #: 38-05255 Rev OHA t RC DOE DATA VALID 50 transition HIGH. 2 CY7C1069AV33 DATA VALID t HZOE t HZSCE HIGH IMPEDANCE 50 Page [+] Feedback ...

Page 6

... CE above is defined as a combination of CE and CE 1 Document #: 38-05255 Rev SCE PWE [16, 17, 18 SCE PWE t t HZWE SD I/O –I/O Mode 0 7 Power-down Power-down Read All Bits Write All Bits Selected, Outputs Disabled . It is active low. 2 CY7C1069AV33 LZWE Power Standby ( Standby ( Active ( Active ( Active ( Page [+] Feedback ...

Page 7

... Ordering Information Speed (ns) Ordering Code 10 CY7C1069AV33-10ZC CY7C1069AV33-10ZXC CY7C1069AV33-10BAC CY7C1069AV33-10ZI CY7C1069AV33-10ZXI CY7C1069AV33-10BAI 12 CY7C1069AV33-12ZC CY7C1069AV33-12ZXC CY7C1069AV33-12BAC CY7C1069AV33-12ZI CY7C1069AV33-12ZXI CY7C1069AV33-12BAI Package Diagrams Document #: 38-05255 Rev. *F Package Diagram Package Type 51-85160 54-pin TSOP II 54-pin TSOP II (Pb-free) 51-85162 60-ball ( 1.2 mm) FBGA 51-85160 54-pin TSOP II 54-pin TSOP II (Pb-free) 51-85162 60-ball ( ...

Page 8

... Cypress against all charges. BOTTOM VIEW A1 CORNER DUMMY BALL (0.3) X12 Ø0. Ø0. Ø0.30±0.05(48X 1.875 A 0.75 0.75 1.00 3.75 6.00 B 8.00±0.10 0.15(4X) CY7C1069AV33 DIMENSIONS IN MM PART # BA60A STANDARD PKG. LEAD FREE PKG. BK60A PKG WEIGHT: 0.30 gms 51-85162-*D Page [+] Feedback ...

Page 9

... Document History Page Document Title: CY7C1069AV33 Static RAM Document Number: 38-05255 Issue REV. ECN NO. Date ** 113724 03/27/02 *A 117060 07/31/02 *B 117990 08/30/02 *C 120385 11/13/02 *D 124441 2/25/03 *E 403984 See ECN *F 492137 See ECN Document #: 38-05255 Rev. *F Orig. of Change Description of Change NSL New Data Sheet ...

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