ISP1161A1 NXP Semiconductors, ISP1161A1 Datasheet
ISP1161A1
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ISP1161A1 Summary of contents
Page 1
... USB host only, a USB device only combination of a configurable USB host and USB device. The ISP1161A1 brings high flexibility to the systems that have it built-in. For example, a system that uses an ISP1161A1 allows it not only to be connected USB hub with a USB downstream port, but also to be connected to a device that has a USB upstream port such as a USB printer, USB camera, USB keyboard or a USB mouse ...
Page 2
... USB I/F Fig 1. ISP1161A1 operating as a USB device. DSC Fig 2. ISP1161A1 operating as a stand-alone USB host. PC (host) USB cable USB I/F Fig 3. ISP1161A1 operating as both USB host and device simultaneously. 9397 750 13961 Product data USB cable USB I/F EMBEDDED SYSTEM P SYSTEM P MEMORY ...
Page 3
... Features 9397 750 13961 Product data Complies with Universal Serial Bus Specification Rev. 2.0 The Host Controller portion of the ISP1161A1 supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) The Device Controller portion of the ISP1161A1 supports data transfer at full-speed (12 Mbit/s) Combines the HC and the single chip On-chip DC complies with most USB device class specifi ...
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... MP3 jukebox Game console. Description plastic low profile quad flat package; 64 leads; body 10 plastic low profile quad flat package; 64 leads; body 7 Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 10 1 1.4 mm © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... H_WAKEUP 42 H_SUSPEND 33 NDP_SEL 14, 16, 17, 63 D15 ISP1161A1 HOST/ 28 DEVICE DACK2 27 AUTOMUX HOST BUS DACK1 34 INTERFACE EOT 26 DREQ2 25 DREQ1 30 INT2 DEVICE BUS 29 INTERFACE INT1 37 D_WAKEUP 36 D_SUSPEND 32 RESET POWER-ON RESET 3 VOLTAGE ...
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... MANAGEMENT REGISTER UNIT ACCESS Host controller sub-blocks INTEGRATED RAM MEMORY P HANDLER MANAGEMENT UNIT EP HANDLER Device controller sub-blocks Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller USB Interface USB STATE clock recovery PHILIPS FRAME SIE MANAGE- MENT PDT_LIST USB ...
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... TTL input; three-state output 5 I/O bit 5 of bidirectional data; slew-rate controlled; TTL input; three-state output Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller ISP1161A1BD ISP1161A1BM © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 48 D_DM 47 H_PSW2 46 H_PSW1 45 DGND ...
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... V or left unconnected. In all cases, decouple this pin to DGND DMA request output (programmable polarity); signals to the DMA controller that the ISP1161A1 wants to start a DMA transfer; see DMA request output (programmable polarity); signals to the DMA controller that the ISP1161A1 wants to start a DMA transfer ...
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... NDP field in the HcRhDescriptorA register; both ports will always be enabled; see (internal pull-up resistor DMA master device to inform the ISP1161A1 of end of DMA transfer; active level is programmable; see Section 10.4 digital ground ‘ ...
Page 10
... I/O bit 1 of bidirectional data; slew-rate controlled; TTL input; three-state output Symbol names with an overscore (e.g. NAME) represent active LOW signals. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller …continued reg(3.3) Table 3 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 11
... DC. 7.5 SoftConnect The connection to the USB is accomplished by bringing D (for full-speed USB devices) HIGH through a 1.5 k pull-up resistor. In the ISP1161A1 DC, the 1.5 k pull-up resistor is integrated on-chip and is not connected to V connection is established through a command sent by the external/system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establish connection with the USB ...
Page 12
... DC has been successfully enumerated (the device address is set), the LED indicator will remain permanently on. Upon each successful packet transfer (with ACK) to and from the ISP1161A1 the LED will blink off for 100 ms. During ‘suspend’ state the LED will remain off. ...
Page 13
... The EOT signal is an external end-of-transfer signal used to terminate the DMA transfer. Some microprocessors may not have this signal. In this case, the ISP1161A1 provides an internal EOT signal to terminate the DMA transfer as well. Setting the HcDMAConfiguration register (21H to read, A1H to write) enables the ISP1161A1 HC internal DMA counter for DMA transfer ...
Page 14
... The ISP1161A1 register structure is a command-data register pair structure. A complete register access cycle comprises a command phase followed by a data phase. The command (also known as the index of a register) points the ISP1161A1 to the next register to be accessed. A command is 8 bits long microprocessor’s 16-bit data bus, a command occupies the lower byte, with the upper byte fi ...
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... Philips Semiconductors Fig 12. 16-bit register access cycle. Most of the ISP1161A1 internal control registers are 16-bit wide. Some of the internal control registers, however, have 32-bit width. control register is accessed. The complete cycle of accessing a 32-bit register consists of a command phase followed by two data phases. In the two data phases, the microprocessor fi ...
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... Fig 15. Accessing DC control registers. 8.4 FIFO buffer RAM access by PIO mode Since the ISP1161A1 internal memory is structured as a FIFO buffer RAM, the FIFO buffer RAM is mapped to dedicated register fields. Therefore, accessing the internal FIFO buffer RAM is similar to accessing the internal control registers in multiple data phases ...
Page 17
... The DMA interface between a microprocessor and the ISP1161A1 is shown in Figure When doing a DMA transfer, at the beginning of every burst the ISP1161A1 outputs a DMA request to the microprocessor via the DREQ pin (DREQ1 for HC, DREQ2 for DC). After receiving this signal, the microprocessor will reply with a DMA acknowledge via the DACK pin (DACK1 for HC, DACK2 for DC), and at the same time, execute the DMA transfer through the data bus ...
Page 18
... In both figures, the hardware is configured such that DREQ is active HIGH and DACK is active LOW. 8.6 Interrupts The ISP1161A1 has separate interrupt request pins for the USB HC (INT1) and the USB DC (INT2). 8.6.1 Pin configuration The interrupt output signals have four configuration modes: ...
Page 19
... INT active INT 166 ns Mode 2 edge triggered, active LOW INT active INT 166 ns Mode 3 edge triggered, active HIGH Rev. 03 — 23 December 2004 ISP1161A1 clear or disable INT clear or disable INT MGT944 Figure 20. © Koninklijke Philips Electronics N.V. 2004. All rights reserved 136 ...
Page 20
... InterruptPinEnable (bit 0 of the HcHardwareConfiguration register). In the event in which the software wishes to temporarily disable the interrupt output of the ISP1161A1 Host Controller, the following procedure should be followed: 1. Make sure that bit InterruptPinEnable in the HcHardwareConfiguration register is 2. Clear all bits in the Hc PInterrupt register. ...
Page 21
... ACK received for an OUT token or transmitted for an IN token. 9397 750 13961 Product data requirements. Table 81). Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Figure 21 shows the relationship Table 83). Default settings © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 22
... Figure A INT2 pin INTENA = 0 (during this time, an interrupt event occurs. For example, SOF asserted.) Pin INT2: HIGH = de-assert; LOW = assert (individual interrupts are enabled). Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller LATCH LE DcMode register INTENA 22 INTENA = 0 ...
Page 23
... When bit INTENA is set to logic 1, pin INT2 is asserted Figure 22): If the firmware sets bit INTENA to logic 0, pin INT2 will still 13.3.6. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Section 13.1.3, Section 13.1.5 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 24
... It is caused by the HostControllerReset field of the HcCommandStatus register (02H to read, 82H to write). 9.2 Generating USB traffic USB traffic can be generated only when the ISP1161A1 USB the USBOperational state. Therefore, the HCD must set the HostControllerFunctionalState field of the HcControl register before generating USB traffi ...
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... Issuing the Resume signal to the HC To generate USB traffic, the HCD must enter the USB transaction loop. The communication between the HCD and the ISP1161A1 the form of Philips Transfer Descriptor (PTD) data. The PTD data provides USB traffic information about the commands, status, and USB data packets. Rev. 03 — ...
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... USB bus interface. The USB transaction status and the feedback from the specified USB device endpoint will be put back into the ISP1161A1 HC internal FIFO buffer RAM in PTD data format. The HCD can read back the PTD data from the internal FIFO buffer RAM ...
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... Product data ActualBytes[7:0] MaxPacketSize[7:0] TotalBytes[7:0] B5_5 reserved FunctionAddress[6:0] reserved Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Active Toggle ActualBytes[9:8] Last Speed MaxPacketSize[9:8] DirectionPID[1:0] TotalBytes[9:8] © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... Specifies the total number of bytes to be transferred with this data structure. For Bulk and Control only, this can be greater than MaxPacketSize. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 29
... This bit is logic 0 at power-on reset. When this feature is not used, software used for the ISP1161A1 is the same for the ISP1160 and the ISP1161. When this bit is set to logic 1 in this PTD for interrupt endpoint transfer, only one PTD USB transaction will be sent out ...
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... ATL buffer ATL bottom Maximum number of useful data sent during one USB frame is 1280 bytes ( 1280 = 1440 bytes 150 1 = 1350 bytes. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller FIFO buffer RAM ISO_A ISO_B programmable sizes data ...
Page 31
... Remark: The PTD is defined for both ATL and ITL type data transfers. For ITL, the PTD data is put into ITL buffer RAM, and the ISP1161A1 takes care of the Ping-Pong action for the ITL buffer RAM access. Fig 27. Buffer RAM data organization. ...
Page 32
... Operation and C program example Figure 29 PIO mode. The ISP1161A1 provides one register as the access port for each buffer RAM. For the ITL buffer RAM, the access port is the ITLBufferPort register (40H to read, C0H to write). For the ATL buffer RAM, the access port is the ATLBufferPort register (41H to read, C1H to write) ...
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... FH incrementing by 1; with values beginning from incrementing by 2. shows the results after running this program. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Commands Command register EOT 2 ...
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... Set the number of bytes to be transferred HcRegWrite(wHcTransferCounter,0x50); wCount = 0x28; // Get word count outport (HcCmdPort,0x00c1); // Command for ATL buffer write 9397 750 13961 Product data USB single-chip host and device controller Rev. 03 — 23 December 2004 ISP1161A1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved 136 ...
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... USB single-chip host and device controller HC initialized and in USBOperational state Yes Rev. 03 — 23 December 2004 ISP1161A1 Comments microprocessor must read ATL transfer completed transfer completed PTD data processed by HC OUT packets can be seen © Koninklijke Philips Electronics N.V. 2004. All rights reserved 136 ...
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... ITL1 buffer because ITL0 and ITL1 are Ping-Pong structured buffers. To recover from this state, a power-on reset or software reset will have to be applied. 9397 750 13961 Product data USB single-chip host and device controller Rev. 03 — 23 December 2004 ISP1161A1 Table 5). © Koninklijke Philips Electronics N.V. 2004. All rights reserved 136 ...
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... AT data (frame N 1) (frame N 2) (Figure 32), the ISO part is still being written while the Start of Frame Rev. 03 — 23 December 2004 ISP1161A1 (frame N 3) MGT954 (frame N 3) MGT955 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 38
... Internal pull-down resistors for downstream ports There are four internal 15 k pull-down resistors built into the ISP1161A1 for the two downstream ports: two resistors for each port. These resistors are software selectable by programming bit 12 (2_DownstreamPort15KresistorSel) of the HcHardwareConfi ...
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... ISP1161A1 bit 12 HcHardware Configuration internal 004aaa180 Using either internal or external 15 k resistors. shows the ISP1161A1 downstream port power management scheme regulator 3 detect H_OCn H_PSWn ‘n’ represents the downstream port number ( Rev. 03 — 23 December 2004 ...
Page 40
... CC . BUS ). For the internal overcurrent detection circuit, OC DSon HC CORE HcHardware Configuration OC select bit Reg PSW C/L ATX SIE bit 12 HcHardware Configuration 15 k ISP1161A1 (2 ) © Koninklijke Philips Electronics N.V. 2004. All rights reserved. . BUS to BUS ) trip of 150 m , the 004aaa182 40 of 136 ...
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... Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller value, an external OC detection circuit can HC CORE HcHardware Configuration OC select bit Reg PSW C/L ATX SIE bit 12 HcHardware Configuration ISP1161A1 004aaa183 © Koninklijke Philips Electronics N.V. 2004. All rights reserved 136 ...
Page 42
... The ISP1161A1 suspend and resume clock scheme is shown in Figure Remark: The ISP1161A1 can only be put into a fully suspended state only after both the HC and the DC go into the suspend state. At this point, the crystal can be turned off and the internal regulator can be put into power-down mode. ...
Page 43
... Philips Semiconductors Wake-up by pin CS (software wake-up): external microprocessor issues a chip select signal through pin CS. This method of access to the ISP1161A1 internal registers is a software wake-up. Wake-up by USB devices: root hub port issues a resume signal to the HC through the USB bus, switching the HC from the USBSuspend state to the USBResume state. This will also set bit ResumeDetected of the HcInterruptStatus register (03H to read, 83H to write) ...
Page 44
... HC Operational registers (32 bits). These operational registers are made compatible to OpenHCI (Host Controller Interface) Operational registers. This allows the OpenHCI HCD to be easily ported to the ISP1161A1. Reserved bits may be defined in future releases of this specification. To ensure interoperability, the HCD must not assume that a reserved field contains logic 0. ...
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... HCI specification that is implemented by this HC. For example, a value of 11H corresponds to version 1.1. All HC implementations that are compliant with this specification will have a value of 10H. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Functionality HC Miscellaneous registers HC Buffer RAM Control registers ...
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... POST. The HC clears the bit upon a hardware reset but does not alter it upon a software reset. Remote wake-up signaling of the host system is host-bus-specific, and is not described in this specification. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 27 26 00H ...
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... The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports. - reserved reserved reserved Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller …continued 27 26 00H © Koninklijke Philips Electronics N.V. 2004. All rights reserved SOC[1:0] ...
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... This bit, when set, does not cause a reset to the Root Hub and no subsequent reset signaling will be asserted to its downstream ports. Section 10.1.5) and bit MasterInterruptEnable is set. The HCD can clear reserved Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 11 10 00H R ...
Page 49
... A scheduling overrun will also cause the SchedulingOverrunCount of HcCommandStatus to be incremented. A bit is set in the HcInterruptStatus register The corresponding bit in the HcInterruptEnable register is set Bit MasterInterruptEnable is set. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 19 18 00H R/W 11 ...
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... Resume Detect SF 0 — ignore 1 — enable interrupt generation due to Start of Frame - reserved SO 0 — ignore 1 — enable interrupt generation due to Scheduling Overrun Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 27 26 reserved 0 0 R/W R/W 19 ...
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... This bit is set after a hardware or software reset. - reserved RHSC 0 — ignore 1 — disable interrupt generation due to Root Hub Status Change Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 27 26 reserved 0 0 R/W ...
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... Scheduling Overrun R/W R FSMPS[7: R/W R FI[7:0] Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller …continued 27 26 FSMPS[14: R/W R 00H R FI[13: R/W R DFH R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... reserved FR[7:0] Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 27 26 reserved 00H FR[13: 00H R © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... FrameNumber: This field is incremented when HcFmRemaining is reloaded. It rolls over to 0000H after FFFFH. When the USBOperational state is entered, this field will be incremented automatically. The HC will set bit StartofFrame in the HcInterruptStatus register. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 27 26 00H R ...
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... LSThreshold: Contains a value that is compared to the FrameRemaining field before a low-speed transaction is initiated. The transaction is started only if FrameRemaining value is calculated by the HCD, which considers transmission and set-up overhead. Default value: 1576 (628H) Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 27 26 00H R/W ...
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... NOCP R reserved Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller R 00H R OCPM R © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... NDP[1:0] NumberDownstreamPorts: These bits specify the number of downstream ports supported by the Root Hub. The maximum number of ports supported by the ISP1161A1 is 2. Rev. 03 — 23 December 2004 ISP1161A1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved 136 ...
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... Product data reserved reserved N/A N reserved reserved N/A N Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller PPCM[2: DR[2:0] N R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
Page 59
... Bit 2 — Device attached to Port # reserved Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller reserved OCIC R reserved ...
Page 60
... PortPowerStatus). In per-port power mode, it clears PortPowerStatus only on ports whose bit PortPowerControlMask is not set. Writing a logic 0 has no effect. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller OCI ...
Page 61
... This bit is set when Root Hub changes the PortOverCurrentIndicator bit. The HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect. 0 — no change in PortOverCurrentIndicator 1 — PortOverCurrentIndicator has changed Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 27 26 00H R/W 19 ...
Page 62
... CurrentConnectStatus is set. 0 — full-speed device attached 1 — low-speed device attached (write) ClearPortPower: The HCD clears bit PortPowerStatus by writing a logic 1 to this bit. Writing a logic 0 has no effect. Rev. 03 — 23 December 2004 ISP1161A1 …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved 136 ...
Page 63
... ClearSuspendStatus: The HCD writes a logic 1 to initiate a resume. Writing a logic 0 has no effect. A resume is initiated only if PortSuspendStatus is set. Rev. 03 — 23 December 2004 ISP1161A1 …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved 136 ...
Page 64
... ClearPortEnable: The HCD writes a logic 1 to this bit to clear bit PortEnableStatus. Writing a logic 0 has no effect. CurrentConnectStatus is not affected by any write. Remark: This bit always reads logic 1 when the attached device is nonremovable (DeviceRemovable[NDP]). Rev. 03 — 23 December 2004 ISP1161A1 …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved 136 ...
Page 65
... DACK1 is used with read and write signals 1 — reserved EOTInputPolarity 0 — active LOW 1 — active HIGH DACKInputPolarity 0 — active LOW 1 — reserved Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Suspend AnalogOC reserved ClkNotStop Enable ...
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... DMA 10 — 8-cycle burst DMA 11 — reserved DMAEnable 0 — DMA is terminated 1 — DMA is enabled. This bit will be reset to zero when DMA transfer is completed. - reserved Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller …continued 11 10 00H R reserved ...
Page 67
... Counter value HcTransferCounter register: bit description Symbol Description Counter The number of data bytes to be read to or written from RAM. value Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller …continued 11 10 00H R 00H R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 68
... AllEOT 0 — no event Interrupt 1 — implies that data transfer has been completed via PIO transfer or DMA transfer. Occurrence of internal or external EOT will set this bit. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 11 10 00H R reserved ...
Page 69
... Interrupt Enable Enable R/W R/W Hc PInterruptEnable register: bit description Symbol Description - reserved ClkReady 0 — power-up value 1 — enables Clkready interrupt Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller …continued Section 11 10 00H R reserved EOT Interrupt Interrupt Enable 0 0 ...
Page 70
... HC miscellaneous registers 10.5.1 HcChipID register (R: 27H) Read this register to get the ID of the ISP1161A1 silicon chip. The higher byte stands for the product name (here 61H stands for the ISP1161A1). The lower byte indicates the revision number of the product including engineering samples. ...
Page 71
... Reset[15: Reset[7:0] HcSoftwareReset register: bit description Symbol Description Reset[15:0] Writing a reset value of F6H will cause the HC to reset all the registers except its buffer memory. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 11 10 00H R 00H R/W 11 ...
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... ITLBufferLength[15: ITLBufferLength[7:0] HcITLBufferLength register: bit description Symbol Description ITLBufferLength[15:0] Assign ITL buffer length ATLBufferLength[15:8] Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 1000H (that is, 4 kbytes 00H R 00H R/W 1000H bytes. For example 00H R/W © ...
Page 73
... Full 1 — ATL Buffer is full ITL1Buffer 0 — 1TL1 Buffer is empty Full 1 — 1TL1 Buffer is full ITL0Buffer 0 — ITL0 Buffer is empty Full 1 — ITL0 Buffer is full Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 3 2 00H R 00H ...
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... RdITL1BufferLength[15: RdITL1BufferLength[7:0] HcReadBackITL1Length register: bit description Symbol RdITL1BufferLength[15:0] The number of bytes for ITL1 data to be read back by Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 11 10 00H 00H R Description The number of bytes for ITL0 data to be read back by ...
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... DataWord[7:0] HcITLBufferPort register: bit description Symbol Description DataWord[15:0] read/write ITL buffer RAM’s two data bytes DataWord[15:8] Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 11 10 00H R 00H R 00H R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 76
... DataWord[7:0] HcATLBufferPort register: bit description Symbol Description DataWord[15:0] read/write ATL buffer RAM’s two data bytes. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 3 2 00H R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved 136 ...
Page 77
... DC data transfer operation The following session explains how the ISP1161A1 handles an IN data transfer and an OUT data transfer. In the Device mode, the ISP1161A1 acts as a USB device data transfer means transfer from the ISP1161A1 to an external USB Host (through the upstream port) and an OUT transfer means transfer from external USB Host to the ISP1161A1 ...
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... SIE at the next OUT token phase. the DMA count is complete bit DMAEN = 0 the DMA controller asserts EOT. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller © Koninklijke Philips Electronics N.V. 2004. All rights reserved 136 ...
Page 79
... The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes. [2] The data flow direction is determined by bit EPDIR in the DcEndpointConfiguration register; see host (ISP1161A1 transmits); OUT: output from the USB host (ISP1161A1 receives). 11.3.3 Endpoint FIFO size The size of the FIFO determines the maximum packet size that the hardware can support for a given endpoint ...
Page 80
... Memory configuration example Logical size (bytes 1023 Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Isochronous 16 bytes 32 bytes 48 bytes 64 bytes 96 bytes 128 bytes 160 bytes 192 bytes 256 bytes ...
Page 81
... IN endpoint to acknowledge success to the host. If there are errors in the endpoint configuration, the firmware must stall the control IN endpoint. When reset by hardware or via the USB bus, the ISP1161A1’s DC disables all endpoints and clears all ECRs, except for the control endpoint which is fixed and always enabled. Endpoint initialization can be done at any time ...
Page 82
... All signals connected to the ISP1161A1 DC must enter appropriate states to meet the power consumption requirements of the suspend state. b. All input pins of the ISP1161A1 DC must have a CMOS LOW or HIGH level. USB bus. When bit BUSTATUS in the DcInterrupt register is logic 0, the USB bus has left the suspend mode and the process must be aborted. Otherwise, the next step can be executed ...
Page 83
... B: indicates resume condition, which can K-state on the USB bus, a HIGH level on pin D_WAKEUP LOW level on pin CS. • C: indicates remote wake-up. The ISP1161A1 will drive a K-state on the USB bus for 10 ms after pin D_WAKEUP goes HIGH or pin CS goes LOW. • ...
Page 84
... The SUSPEND output is deasserted, and bit RESUME in the DcInterrupt register 3. Maximum 15 ms after starting the wake-up sequence, the ISP1161A1 case of a remote wake-up, the ISP1161A1 DC drives a K-state on the USB bus 5. Following the deassertion of output SUSPEND, the application restores itself and 6 ...
Page 85
... Many different implementations of DMA exist. The ISP1161A1 DC supports two methods: • • The ISP1161A1’s DC supports DMA transfer for all 14 configurable endpoints (see Table operation of the ISP1161A1’s DC can be interleaved with normal I/O mode access to other endpoints. The following features are supported: • • • ...
Page 86
... It operates as a ‘fly-by’ DMA controller: the data is not stored in the DMA controller, but it is transferred between an I/O port and a memory address. A typical example of the ISP1161A1’ 8237 compatible DMA mode is given in The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and DACK (DMA Acknowledge) ...
Page 87
... After completing the current instruction cycle, the CPU places the bus control 5. The 8237 now sets its address lines to 1234H and activates the MEMW and IOR 6. The 8237 asserts DACK to inform the ISP1161A1’s DC that it will start a DMA 7. The ISP1161A1’s DC now places the word to be transferred on the data bus 8. The 8237 waits one DMA clock period and then de-asserts MEMW and IOR. This 9. The ISP1161A1’ ...
Page 88
... EOT the DACK-only mode, the ISP1161A1’s DC uses the DACK2 signal as a data strobe. Input signals RD and WR are ignored. This mode is used in CPU systems that have a single address space for memory and I/O access. Such systems have no separate MEMW and MEMR signals: the RD and WR signals are also used as memory data strobes. Fig 41. ISP1161A1’ ...
Page 89
... Philips Semiconductors DcDMACounter register: setting bit CNTREN in the DcDMAConfiguration register. The ISP1161A1 has a 16-bit DcDMACounter register, which specifies the number of bytes to be transferred. When DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value from the DcDMACounter register. When the internal counter completes the transfer as programmed in the DcDMACounter, an EOT condition is generated and the DMA operation stops ...
Page 90
... Philips Semiconductors 13. DC commands and registers The functions and registers of the ISP1161A1’s DC are accessed via commands, which consist of a command code followed by optional data bytes (read or write action). An overview of the available commands and registers is given in A complete access consists of two phases: 1 ...
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... Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller [1] Transaction Reference write/read 1 word Section 13.1.7 on page 98 - Section 13.1.8 on page 99 - Section 13.2.1 on page bytes isochronous: N 1023 bytes interrupt/bulk bytes ...
Page 92
... Initialization commands are used during the enumeration process of the USB network. These commands are used to configure and enable the embedded endpoints. They also serve to set the USB assigned address of the ISP1161A1’s DC and to perform a device reset. 13.1.1 DcEndpointConfiguration register (R/W: 30H–3FH/20H–2FH) This command is used to access the Endpoint Confi ...
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... Selects the FIFO size according to 78 R/W R/W DcAddress register: bit description Symbol Description DEVEN A logic 1 enables the device. DEVADR[6:0] This field specifies the USB device address. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 3 2 FFOSZ[3: R/W R/W R/W Table DEVADR[6: R/W R/W R/W © ...
Page 94
... Philips Semiconductors 13.1.3 DcMode register (R/W: B9H/B8H) This command is used to access the ISP1161A1’s DcMode register, which consists of 1 byte (for bit allocation: see ignored. The DcMode register controls the DMA bus width, resume and suspend modes, interrupt activity and SoftConnect operation. It can be used to enable debug mode, where all errors and Not Acknowledge (NAK) conditions will generate an interrupt. Code (Hex): B8/B9 — ...
Page 95
... HIGH). Bus reset value: unchanged. DAKPOL Selects DACK2 pin signal polarity (0 = active LOW). Bus reset value: unchanged. EOTPOL Selects EOT pin signal polarity (0 = active LOW active HIGH). Bus reset value: unchanged. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller CLKDIV[3: ...
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... INT2 pin interrupt event occurs Pin INT2: HIGH = de-assert; LOW = assert; INTENA = 1. Table 84. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller …continued must be present for wake-up on CS). Section 8.6.3 for details. register enabled interrupt is cleared interrupt event ...
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... DcDMAConfiguration register (R/W: F1H/F0H) This command defines the DMA configuration of the ISP1161A1’s DC and enables/disables DMA transfers. The command accesses the DcDMAConfiguration register, which consists of 2 bytes. The bit allocation is given in will clear bit DMAEN (DMA disabled), all other bits remain unchanged. ...
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... Bus reset value: unchanged. 88. Writing to the register sets the number of bytes for a DMA transfer. Reading Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller reserved reserved ...
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... Table 89: Bit 13.1.8 Reset Device (F6H) This command resets the ISP1161A1 DC in the same way as an external hardware reset via input RESET. All registers are initialized to their ‘reset’ values. Code (Hex): F6 — reset the device Transaction — none 13.2 Data flow commands Data fl ...
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... Philips Semiconductors Remark: Reading data after a Write Endpoint Buffer command or writing data after a Read Endpoint Buffer command will cause unpredictable behavior of the ISP1161A1 DC. Code (Hex — write (control IN, endpoint 1 to 14) Code (Hex): 10 — read (control OUT, endpoint 1 to 14) Transaction — ...
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... SETUPT A logic 1 indicates that the buffer contains a Setup packet. CPUBUF This bit indicates which buffer is currently selected for CPU access (0 = primary buffer secondary buffer). - reserved Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller OVER SETUPT CPUBUF WRITE ...
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... A logic 1 indicates that the secondary endpoint buffer is full. EPFULL0 A logic 1 indicates that the primary endpoint buffer is full. DATA_PID This bit indicates the data PID of the next packet (0 = DATA PID DATA1 PID). Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Section Section ...
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... A logic 1 indicates that a new event occurred before the previous status was read. DATA01 This bit indicates the PID type of the last successfully received or transmitted packet (0 = DATA0 PID DATA1 PID). Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller …continued Section 3 2 ...
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... Unlock Device (B0H) This command unlocks the ISP1161A1’s DC from write-protection mode after a ‘resume’. In ‘suspend’ state all registers and FIFOs are write-protected to prevent data corruption by external devices during a ‘resume’. Also, the register access for reading is possible only after the ‘Unlock Device’ command is executed. ...
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... R/W R SFIRL[7:0] Symbol Description - reserved; must be logic 0 SFIR[12:0] Scratch Information register Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 3 2 37H W Table 11 10 SFIRH[4: R/W R 00H R/W Table © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 106
... SOFRH[2:0] SOF frame number (upper byte) SOFRL[7:0] SOF frame number (lower byte) Phase Bus lines command D[7:0] D[15:8] data D[15:0] 106 CHIPIDH[7: CHIPIDL[7:0] Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 11 10 SOFRH[2: Word # Description - command code (B4H) ...
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... A logic 1 indicates the interrupt source: control OUT endpoint. BUSTATUS Monitors the current USB bus status (0 = awake suspend). SP_EOT A logic 1 indicates that an EOT interrupt has occurred for a short packet. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 108. Bit BUSTATUS is used to verify the current 13.1.5. Section 8.6.3. 27 ...
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... A logic 1 indicates that an ‘awake’ to ‘suspend’ change of state was detected on the USB bus. RESUME A logic 1 indicates that a ‘resume’ state was detected. RESET A logic 1 indicates that a bus reset condition was detected. Rev. 03 — 23 December 2004 ISP1161A1 …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 108 of 136 ...
Page 109
... Philips Semiconductors 14. Power supply The ISP1161A1 can operate at either 3.3 V. When using the ISP1161A1’s power supply input, only V connected to the 5 V power supply. An application with power supply input is shown in 3.3 V for its internal core. This internal 3.3 V can also be obtained from V (pin 58) to supply the 1.5 k pull-up resistor of the DC side upstream port signal D_DP. The signal D_DP is connected to the standard USB upstream port connector’ ...
Page 110
... Product data MHz 18 pF 004aaa190 Fig 46. Oscillator circuit using external oscillator. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller MHz ISP1161A1 Out CLKOUT OSC n.c. XTAL2 XTAL1 004aaa191 50 %. Figure 47. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 111
... NOLAZY controls the LazyClock signal output during ‘suspend’ state. For details about the DC’s interrupt logic, see When the ISP1161A1’s DC enters the ‘suspend’ state (by setting and clearing bit GOSUSP in the DcMode register), outputs D_SUSPEND and CLKOUT change state after approximately 2 ms delay. When NOLAZY = 0 the clock signal on output CLKOUT does not stop, but changes to the 100 kHz When resuming from ‘ ...
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... PORP = power-on reset pulse. shows the availability of the clock with respect to the external POR. POR EXTERNAL CLOCK Stable external clock is available at A. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller is 3 depends on how fast V CC Figure 49 shows a possible curve of ...
Page 113
... V tolerant. 9397 750 13961 Product data Conditions CC reg(3.3) V < > < Conditions with internal regulator internal regulator bypass Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Min Max 0.5 6.0 0.5 4.6 0.5 6.0 - 100 CC [1] 2000 2000 60 150 ...
Page 114
... amb = unless otherwise specified. GND amb Conditions [ Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller [1] Min Typ Max [2] 3.0 3.3 3 500 - ...
Page 115
... V V I(D ) I(D ) range 1 3 GND pin to GND enable internal resistors SoftConnect = ON steady-state drive both H_D and H_D . Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Min Typ Max [ Min Typ Max [ ...
Page 116
... GND amb Conditions pF pF Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Min Typ Max 160 - - [ 100 - 500 ...
Page 117
... If you are accessing only the HC, then the HC Programmed I/O timing applies. If you are accessing only the DC, then the DC Programmed I/O timing applies. If you are accessing both the HC and the DC, then the DC Programmed I/O timing applies. Conditions Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Min Typ Max 5 ...
Page 118
... CS HIGH SHDZ t chip deselect time after RD HIGH RHSH t RD pulse width RLRH t data valid time after RD LOW RLDV t CS HIGH until next ISP1161A1 RD SHRL read cycle time SHRL RLRH Write timing (see Figure 53) t address hold time after WR HIGH ...
Page 119
... RHAX t AVRL t SHDZ (1) t RLRH t SHRL t RHSH t WHAX t AVWL t WLWH (1) t SHWL t WHSH t WHDZ Conditions Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Min Typ Max © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 004aaa105 004aaa106 Unit ns ...
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... DREQ1 HIGH to DACK1 LOW SLAL 9397 750 13961 Product data …continued Conditions ALRL t RHAL t RLDV t RHDZ data valid data valid t WSU t WHD Conditions Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Min Typ Max ...
Page 121
... Fig 55. HC burst mode DMA timing. 9397 750 13961 Product data …continued Conditions 4-cycle burst mode 8-cycle burst mode 4-cycle burst mode 8-cycle burst mode t RHRL RLRH Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Min Typ Max [ 105 - - 150 ...
Page 122
... DREQ1 DACK1 EOT t RLIS 0 ns DREQ1 DACK1 EOT t RLIS 0 ns Conditions ASRP Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Min Typ Max - - 40 180 - - © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 004aaa109 004aaa110 Unit ns ...
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... Product data USB single-chip host and device controller Conditions Min - 25 180 - - t ASRP t ASAP t APDZ t ASDV Conditions Min - 180 ASAP t ASRP t ASDV Rev. 03 — 23 December 2004 ISP1161A1 Typ Max Unit - APRS 004aaa112 Typ Max Unit ...
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... DMA burst repeat interval (input IHIL RD/WR HIGH to LOW) 9397 750 13961 Product data USB single-chip host and device controller Conditions EOT on; DACK on; RD/WR LOW t RSIH t ASRP t IHAP (1) t RLIS t EOT t WLIS (3) Conditions Rev. 03 — 23 December 2004 ISP1161A1 Min Typ Max 004aaa114 ...
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... Fig 63. EOT timing in DC burst mode DMA. 9397 750 13961 Product data USB single-chip host and device controller t RSIH t IHIL Conditions EOT on; DACK on; RD/WR LOW t ISRP t RLIS t WLIS (1) t EOT Rev. 03 — 23 December 2004 ISP1161A1 t ILRP t IHAP 004aaa115 Min Typ Max ...
Page 126
... DSon (2) 470 assuming that Fig 64. Typical interface circuit to Hitachi SH-3 (SH7709) RISC processor. 9397 750 13961 Product data USB single-chip host and device controller Rev. 03 — 23 December 2004 ISP1161A1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 126 of 136 ...
Page 127
... DC/DC regulator will be bypassed best to connect all four power supply pins (V CC Section ISP1161A1 the flexibility to be used in an embedded system under either a 3 power supply. A typical SH7709 interface circuit is shown in 21.3 Typical software model This section shows a typical software requirement for an embedded system that incorporates the ISP1161A1 ...
Page 128
... DEVICE DRIVERS MASS STORAGE CLASS DRIVER PRINTING CLASS DRIVER RISC ROM ISP1161A1 RAM LEN CONTROL Fig 65. ISP1161A1 software model for DSC application. 9397 750 13961 Product data FILE TRANSFER HOST STACK DEVICE STACK ISP1161A1 HAL Digital Still Camera Rev. 03 — 23 December 2004 ...
Page 129
... Product data were determined using the circuit shown in D.U.T. Load capacitance (full-speed mode). L Speed: full-speed mode only: internal 1.5 k pull-up resistor on D_DP. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller as listed in Figure 66. test point MGT967 © ...
Page 130
... 0.27 0.18 10.1 10.1 12.15 12.15 0.5 0.17 0.12 9.9 9.9 11.85 11.85 REFERENCES JEDEC JEITA MS-026 Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller detail 0.75 1.45 1 0.2 0.12 0.1 0.45 1.05 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 131
... 0.23 0.20 7.1 7.1 9.15 9.15 0.4 0.13 0.09 6.9 6.9 8.85 8.85 REFERENCES JEDEC JEITA MS-026 Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller detail 0.75 0.64 1 0.2 0.08 0.08 0.45 0.36 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 132
... C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 2.5 mm 350 called small/thin packages. © ...
Page 133
... For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods . Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller Soldering method Wave ...
Page 134
... SHWL Product data (9397 750 11828) Product data (9397 750 10241) Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller 10 C measured in the atmosphere of the reflow circuit”: fourth paragraph, second timing”: changed the from ns, and added t WHAX © ...
Page 135
... SoftConnect — trademark of Koninklijke Philips Electronics N.V. StrongARM — registered trademark of ARM Ltd. SuperH — trademark of Hitachi Ltd. Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Fax: + 24825 ...
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... Static characteristics . . . . . . . . . . . . . . . . . . 114 20 Dynamic characteristics . . . . . . . . . . . . . . . . 116 20.1 Programmed I/O timing . . . . . . . . . . . . . . . . 117 20.2 DMA timing 119 21 Application information . . . . . . . . . . . . . . . . 126 21.1 Typical interface circuit . . . . . . . . . . . . . . . . . 126 21.2 Interfacing a ISP1161A1 with a SH7709 RISC processor 127 21.3 Typical software model . . . . . . . . . . . . . . . . . 127 22 Test information 129 23 Package outline . . . . . . . . . . . . . . . . . . . . . . . 130 24 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 24.1 Introduction to soldering surface mount packages ...