ISP1161BD NXP Semiconductors, ISP1161BD Datasheet
ISP1161BD
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ISP1161BD Summary of contents
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ISP1161 Full-speed Universal Serial Bus single-chip host and device controller Rev. 01 — 3 July 2001 1. General description The ISP1161 is a single-chip Universal Serial Bus (USB) Host Controller (HC) and Device Controller (DC) which complies with Universal Serial ...
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Philips Semiconductors Fig 1. ISP1161 operating as a USB device. Fig 2. ISP1161 operating as a stand-alone USB host. 9397 750 08313 Product data Full-speed USB single-chip host and device controller PC (host) USB cable USB I/F USB I/F EMBEDDED ...
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Philips Semiconductors PC (host) USB cable USB I/F Fig 3. ISP1161 operating as both USB host and device simultaneously. 2. Features Complies with Universal Serial Bus Specification Rev 1.1 Combines HC and single chip On-chip DC complies ...
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... Ordering information Table 1: Ordering information Type number Package Name Description ISP1161BD LQFP64 Plastic low profile quad flat package; 64 leads; body 1.4 mm ISP1161BM LQFP64 Plastic low profile quad flat package; 64 leads; body 1.4 mm 9397 750 08313 Product data Full-speed USB single-chip host and device controller Rev. 01 — ...
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H_WAKEUP 42 H_SUSPEND 33 NDP_SEL 14, 16, 17, 63 D15 ISP1161 HOST/ 28 DEVICE DACK2 27 AUTOMUX ...
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Philips Semiconductors POWER-ON RESET P interface DMA HANDLER Host bus I/F P HANDLER Fig 5. Host controller sub block diagram. POWER-ON RESET Device BUS I/F bus I/F Fig 6. Device controller sub block diagram. 9397 750 08313 Product data Full-speed ...
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... Fig 7. Pin configuration LQFP64. 6.2 Pin description Table 2: Symbol DGND 9397 750 08313 Product data Full-speed USB single-chip host and device controller ISP1161BD ISP1161BM Pin description for LQFP64 [1] Pin Type Description 1 - digital ground 2 I/O bit 2 of bidirectional data ...
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Philips Semiconductors Table 2: Symbol D6 D7 DGND D8 D9 D10 D11 D12 D13 DGND D14 D15 DGND V hold1 n. hold2 DREQ1 9397 750 08313 Product data Full-speed USB single-chip host and device controller Pin ...
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Philips Semiconductors Table 2: Symbol DREQ2 DACK1 DACK2 INT1 INT2 TEST RESET NDP_SEL EOT DGND D_SUSPEND D_WAKEUP GL D_VBUS H_WAKEUP CLKOUT H_SUSPEND XTAL1 9397 750 08313 Product data Full-speed USB single-chip host and device controller Pin description for LQFP64 …continued ...
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Philips Semiconductors Table 2: Symbol XTAL2 DGND H_PSW1 H_PSW2 D_DM D_DP H_DM1 H_DP1 H_DM2 H_DP2 H_OC1 H_OC2 V CC AGND V reg(3. n.c. DGND D0 D1 [1] Symbol names with an overscore (e.g. NAME) represent active LOW signals. ...
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Philips Semiconductors 7. Functional description 7.1 PLL clock multiplier MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external components ...
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Philips Semiconductors 7.6 GoodLink (in DC) Indication of a good USB connection is provided at pin GL through GoodLink technology. During enumeration the LED indicator will blink on momentarily. When the ISP1161 has been successfully enumerated (the device address is ...
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Philips Semiconductors microprocessors can read or write ISP1161’s internal control registers and FIFO buffer RAM through the parallel I/O (PIO) operating mode. I/O interface between a microprocessor and ISP1161. Fig 9. Parallel I/O interface between microprocessor and ISP1161. 8.2 DMA ...
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Philips Semiconductors Fig 10. DMA interface between microprocessor and ISP1161. 8.3 Microprocessor read/write ISP1161’s internal control registers by PIO mode 8.3.1 I/O port addressing Table 3 address should include the chip select signal CS and the address lines A1 and ...
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Philips Semiconductors When microprocessor accesses the HC. When microprocessor accesses the DC. Fig 11. A microprocessor accessing via an automux switch. When microprocessor accesses the data ...
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Philips Semiconductors For ISP1161’s ES1 (engineering sample: version one), the chip’ 6110H, where the upper byte of 61H stands for ISP1161, and the lower byte of 10H stands for the first version of the IC chip. Fig 13. ...
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Philips Semiconductors Signals CS A1, A0 RD, WR data bus Fig 16. Accessing ISP1161 DC control registers. 8.4 Microprocessor read/write ISP1161’s internal FIFO buffer RAM by PIO mode Since ISP1161’s internal memory is structured as a FIFO buffer RAM, the ...
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Philips Semiconductors microprocessor must still issue signal to ISP1161’ pin. (DACK Only mode does not need the signal.) ISP1161 will repeat the DMA cycles until it receives an EOT signal ...
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Philips Semiconductors 8.6 Interrupts ISP1161 has separate interrupt request pins for the USB HC (INT1) and the USB DC (INT2). 8.6.1 Pin configuration The interrupt output signals have four configuration modes: • Level trigger, active LOW • Level trigger, active ...
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Philips Semiconductors HcInterruptStatus register FNO RHSC FNO IE RHSC IE HcInterruptEnable register Fig 21. HC interrupt logic. The interrupt events of the Hc PInterrupt register (24H ...
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Philips Semiconductors Bits RESET, RESUME, EOT and SOF are cleared upon reading the Interrupt Register. The endpoint bits (EP0OUT to EP14) are cleared by reading the associated Endpoint Status Register. Bit BUSTATUS follows the USB bus status exactly, allowing the ...
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Philips Semiconductors 9. The USB host controller (HC) 9.1 The HC’s four USB states ISP1161’s USB HC has four USB states USB Operational, USB Reset, USB Suspend, and USB Resume that define the HC’s USB signaling and bus states responsibilities. ...
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Philips Semiconductors A simplistic flow diagram showing when and how to generate USB traffic is shown in Figure Revision 1.1 about the protocol and ISP1161 USB HC’s register usage. Reset HC state = USB_Operational Initialize HC Entry Fig 24. ISP1161 ...
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Philips Semiconductors • Prepare PTD Data in P System RAM The communication channel between the HC Driver and ISP1161’s USB the form of Philips Transfer Descriptor (PTD) data. The PTD data provides USB traffic information about the ...
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Philips Semiconductors The PTD data structure is used by the HC to define a buffer of data that will be moved to or from an endpoint in the USB device. This data buffer is set up for the current frame ...
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Philips Semiconductors Table 5: Philips Transfer Descriptor (PTD): bit description Symbol Access ActualBytes[9:0] R/W Contains the number of bytes that were transferred for this PTD CompletionCode[3:0] R/W 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 ...
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Philips Semiconductors Table 5: Philips Transfer Descriptor (PTD): bit description Symbol Access TotalBytes[9:0] R Specifies the total number of bytes to be transferred with this data structure. For Bulk and Control only, this can be greater than MaximumPacketSize. DirectionPID[1:0] R ...
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Philips Semiconductors • ATL buffer length = 400H, ITL buffer length = 200H. This is insufficient use of the internal FIFO buffer RAM. • ATL buffer length = 1000H, ITL buffer length = 0H. This will use the internal FIFO ...
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Philips Semiconductors The data transfer can be done via PIO mode or DMA mode. The data transfer rate can Mbyte/s. In DMA operation, single-cycle or multi-cycle burst modes are supported. For the multi-cycle burst mode, 1, ...
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Philips Semiconductors Fig 28. PTD data with DWORD alignment in buffer RAM. 9.4.3 Operation & C Program Example Figure 29 mode. ISP1161 provides one register as the access port for each buffer RAM. For the ITL buffer RAM, the access ...
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Philips Semiconductors Following is an example program that shows how to write data into the ATL buffer RAM. The total number of data bytes to be transferred is 80 (decimal) which will be set into the HcTransferCounter ...
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Philips Semiconductors unsigned int i; unsigned int wCount,wData; // Prepare PTD data to be written into HC ATL buffer RAM: unsigned int PTDData[0x28]= { 0x0800,0x1010,0x0810,0x0005, //PTD header for IN token #1 //Reserved space for payload data of IN token #1 ...
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Philips Semiconductors return(wValue Write HC 16-bit registers // void HcRegWrite(unsigned int wIndex,unsigned int wValue) { outport(HcCmdPort,wIndex | 0x80); outport(HcDataPort,wValue Host bus I 000H 001H 3FFH ITL0 buffer RAM (8-bit width) Fig 29. PIO ...
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Philips Semiconductors One interrupt is issued concurrently with the SOF. This interrupt (the ITLint is set in the Hc PInterrupt register) triggers reading and writing of the ITL by the microprocessor, after which the interrupt is cleared by the microprocessor. ...
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Philips Semiconductors • The ISO packet for frame will be written; • The AT packet for frame will be written. traffic SOF on USB (frame N) ISO interrupt read ISO_A(N 1) write ISO_A(N 1) ...
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Philips Semiconductors (frame N) Fig 32. HC time domain behavior: example 3. Control Transaction Limitations The different phases of a Control transfer (SETUP, Data and Status) should never be put in the same ATL. 9.6 Microprocessor loading The maximum amount ...
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Philips Semiconductors Using either internal or external 15 k resistors. Fig 33. Use pull-down resistors on downstream ports. 9.8 Overcurrent detection and power switching control A downstream port provides +5 V power supply to the V hardware ...
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Philips Semiconductors 9.8.1 Using internal OC detection circuit The internal OC detection circuit can be used only when power supply. The HC Driver must set AnalogOCEnable, bit 10 of the HcHardwareConfiguration register, to logic 1. An ...
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Philips Semiconductors BUS V BUS USB downstream port connector 22 22 Fig 35. Using internal OC detection circuit. 9.8.2 Using external OC detection circuit When V power supply, then the internal OC detection ...
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Philips Semiconductors V BUS external OC detect USB downstream port connector 22 22 Fig 36. Using external OC detection circuit. 10. Suspend and wakeup (in HC) 10.1 HC suspended state The HC can be ...
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Philips Semiconductors With the device in a suspended state it will consume considerably less power by turning off the internal 48 MHz clock, PLL and crystal, and setting the internal regulator to power-down mode. The ISP1161 suspend and resume clock ...
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Philips Semiconductors No matter which method is used to wake up the HC from SUSPEND state, you must enable the corresponding interrupt bits before the HC goes into SUSPEND state so that the microprocessor can receive the correct interrupt request ...
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Philips Semiconductors 11.1.2 OUT data transfer • The arrival of the OUT token is detected by the SIE by decoding the PID. • The SIE also checks for the device number and endpoint number and verifies whether they are ok. ...
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Philips Semiconductors When the DMA controller terminates the DMA transfer by asserting EOT and Auto-reload mode is off, the buffer is also cleared (even if not all data are read) and the DMA handler is disabled automatically. For the next ...
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Philips Semiconductors [1] IN: input for the USB host (ISP1161 transmits); OUT: output from the USB host (ISP1161 receives). [2] The data flow direction is determined by bit EPDIR in the Endpoint Configuration Register. [3] The total amount of FIFO ...
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Philips Semiconductors Table 8: FFOSZ[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Each programmable FIFO can be configured independently via its ECR, but the total physical size of all enabled endpoints ...
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Philips Semiconductors 11.3.4 Endpoint initialization In response to the standard USB request Set Interface, the firmware must program all 16 ECRs of the ISP1161 in sequence (see enabled or not. The hardware will then automatically allocate FIFO storage space. If ...
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Philips Semiconductors 12. DMA transfer for the Device Controller Direct Memory Access (DMA method to transfer data from one location to another in a computer system, without intervention of the Central Processor Unit (CPU). Many different implementations of ...
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Philips Semiconductors Table 10: Endpoint selection for DMA transfer Endpoint identifier 12.2 8237 compatible mode The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware Configuration Register (see Table Table 11: 8237 compatible mode: pin functions ...
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Philips Semiconductors The following example shows the steps which occur in a typical DMA transfer: 1. ISP1161 DC receives a data packet in one of its endpoint FIFOs; the packet must be transferred to memory address 1234H. 2. ISP1161 DC ...
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Philips Semiconductors Table 12: DACK-only mode: pin functions Symbol EOT DACK-only mode the ISP1161 DC uses the DACK2 signal as a data strobe. Input signals RD and WR are ignored. This mode is used in CPU systems ...
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Philips Semiconductors DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value from the DMA Counter Register. When the internal counter reaches zero an EOT condition is generated and the DMA operation stops. Short/empty packet: ...
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Philips Semiconductors 13. HC registers The HC contains a set of on-chip control registers. These registers can be read or written by the Host Controller Driver (HCD). The Control and Status register sets, Frame Counter register sets, and Root Hub ...
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Philips Semiconductors Table 15: HC Control Register summary Command (Hex) Read 13.1 HC control and status registers 13.1.1 HcRevision Register Table 16: HcRevision Register: bit allocation Bit 31 30 Symbol ...
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Philips Semiconductors Code (Hex): 00 — read only 13.1.2 HcControl Register The HcControl register defines the operating modes for the HC. Most fields are modified only by the HCD, except for HostControllerFunctionalState (HCFS) and RemoteWakeupConnected (RWC). Table 18: HcControl Register: ...
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Philips Semiconductors Table 19: HcControl Register: bit description Bit Code (Hex): 01 — read Code (Hex): 81 — write 13.1.3 HcCommandStatus Register The HcCommandStatus register is used by ...
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Philips Semiconductors The SchedulingOverrunCount field indicates the number of frames with which the HC has detected the scheduling overrun error. This occurs when the Periodic list does not complete before EOF. When a scheduling overrun error is detected, the HC ...
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Philips Semiconductors 13.1.4 HcInterruptStatus Register This register provides the status of the events that cause hardware interrupts. When an event occurs, the HC sets the corresponding bit in this register. When a bit becomes set, a hardware interrupt is generated ...
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Philips Semiconductors Table 23: HcInterruptStatus Register: bit description Bit Code (Hex): 03 — read Code (Hex): 83 — write 13.1.5 HcInterruptEnable Register Each enable bit in the HcInterruptEnable register ...
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Philips Semiconductors Table 24: HcInterruptEnable Register: bit allocation Bit 31 30 Symbol MIE Reset 0 0 Access Bit 23 22 Symbol Reset Access Bit 15 14 Symbol Reset Access Bit 7 6 Symbol reserved RHSC Reset 0 0 Access Table ...
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Philips Semiconductors 13.1.6 HcInterruptDisable Register Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the HcInterruptEnable register. Thus, writing a logic bit in ...
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Philips Semiconductors Table 27: HcInterruptDisable Register: bit description Bit Code (Hex): 05 — read Code (Hex): 85 — write 13.2 HC frame counter registers 13.2.1 HcFmInterval Register The HcFmInterval register contains a 14-bit value ...
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Philips Semiconductors Table 29: HcFmInterval Register: bit description Bit Code (Hex): 0D — read Code (Hex): 8D — write 13.2.2 HcFmRemaining Register The HcFmRemaining register is a 14-bit down counter ...
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Philips Semiconductors Table 31: HcFmRemaining Register: bit description Bit Code (Hex): 0E — read 13.2.3 HcFmNumber Register The HcFmNumber register is a 16-bit counter. It provides a timing reference for events happening in ...
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Philips Semiconductors Table 33: HcFmNumber Register: bit description Bit Code (Hex): 0F — read 13.2.4 HcLSThreshold Register The HcLSThreshold register contains an 11-bit value used by the HC to determine whether to commit to ...
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Philips Semiconductors Code (Hex): 11 — read Code (Hex): 91 — write 13.3 HC Root Hub registers All registers included in this partition are dedicated to the USB Root Hub, which is an integral part of the HC although it ...
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Philips Semiconductors Table 36: HcRhDescriptorA Register: bit description Bit 31 30 Symbol Reset Access Bit 23 22 Symbol Reset Access Bit 15 14 Symbol reserved Reset 0 0 Access R/W Bit 7 6 Symbol Reset Access 9397 750 08313 Product ...
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Philips Semiconductors Table 37: HcRhDescriptorA Register: bit description Bit Code (Hex): 12 — read Code (Hex): 92 — write 9397 750 08313 Product data Full-speed USB ...
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Philips Semiconductors 13.3.2 HcRhDescriptorB Register The HcRhDescriptorB register is the second register of two describing the characteristics of the Root Hub. These fields are written during initialization to correspond with the system implementation. Reset values are implementation-specific (IS). Table 38: ...
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Philips Semiconductors Code (Hex): 13 — read Code (Hex): 93 — write 13.3.3 HcRhStatus Register The HcRhStatus register is divided into two parts. The lower word of a Dword represents the Hub Status field and the upper word represents the ...
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Philips Semiconductors Table 41: HcRhStatus Register: bit description Bit Code (Hex): 14 — read Code (Hex): 94 — write 9397 750 08313 Product data Full-speed USB single-chip host ...
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Philips Semiconductors 13.3.4 HcRhPortStatus[1:2] The HcRhPortStatus[1:2] register is used to control and report port events on a per-port basis. NumberDownstreamPorts represents the number of HcRhPortStatus registers that are implemented in hardware. The lower word is used to reflect the port ...
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Philips Semiconductors Table 43: HcRhPortStatus[1:2] Register: bit description Bit 9397 750 08313 Product data Full-speed USB single-chip host and device controller Symbol Description - reserved PRSC PortResetStatusChange: This ...
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Philips Semiconductors Table 43: HcRhPortStatus[1:2] Register: bit description Bit 9397 750 08313 Product data Full-speed USB single-chip host and device controller Symbol Description PPS (read) PortPowerStatus: This bit reflects the port power status, regardless ...
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Philips Semiconductors Table 43: HcRhPortStatus[1:2] Register: bit description Bit Code (Hex): [1] = 15, [ — read Code (Hex): [1] = 95, [ — write 9397 750 08313 Product data Full-speed USB single-chip ...
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Philips Semiconductors 13.4 HC DMA and interrupt control registers 13.4.1 HcHardwareConfiguration Register Table 44: HcHardwareConfiguration Register: bit allocation Bit 15 14 Symbol reserved Reset 0 0 Access R/W Bit 7 6 Symbol EOTInput DACKInput Polarity Polarity Reset 0 0 Access ...
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Philips Semiconductors Code (Hex): 20 — read Code (Hex): A0 — write Remark: 1. Bit 0, InterruptPinEnable, is used as pin INT1’s master interrupt enable. This bit should be used together with the register Hc PInterruptEnable to enable pin INT1. ...
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Philips Semiconductors 13.4.3 HcTransferCounter Register This register holds the number of bytes of a PIO or DMA transfer. For a PIO transfer, the number of bytes being read or written to the (Isochronous Transfer List) ITL or (Acknowledged Transfer List) ...
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Philips Semiconductors Table 50: Hc PInterrupt Register: bit allocation Bit 15 14 Symbol Reset Access Bit 7 6 Symbol reserved ClkReady Reset 0 0 Access Table 51: Hc PInterrupt Register: bit description Bit ...
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Philips Semiconductors 13.4.5 HcuPInterruptEnable Register The bits 6:0 in this register are the same as those in the Hc PInterrupt register. They are used together with bit 0 of the HcHardwareConfiguration register to enable or disable the bits in the ...
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Philips Semiconductors Code (Hex): 25 — read Code (Hex): A5 — write 13.5 HC miscellaneous registers 13.5.1 HcChipID Register Read this register to get the ID of the ISP1161 silicon chip. The high byte stands for the product name (here ...
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Philips Semiconductors Code (Hex): A8 — write 13.5.3 HcSoftwareReset Register This is a soft reset command. The microprocessor writes A9H to ISP1161’s command port, resetting all the HC’s internal registers except for the internal FIFO buffer RAM. Table 58: HcSoftwareReset ...
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Philips Semiconductors Table 61: HcITLBufferLength Register: bit description Bit Code (Hex): 2A — read Code (Hex): AA — write 13.6.2 HcATLBufferLength Register Write to this register to assign ATL buffer size. Table 62: HcATLBufferLength Register: bit allocation ...
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Philips Semiconductors Table 65: HcBufferStatus Register: bit description Bit Code (Hex): 2C — read 13.6.4 HcReadBackITL0Length Register This register’s value stands for the current number of data bytes ...
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Philips Semiconductors Table 68: HcReadBackITL1Length Register: bit allocation Bit 15 14 Symbol Reset 0 0 Access Bit 7 6 Symbol Reset 0 0 Access Table 69: HcReadBackITL1Length Register: bit description Bit Code (Hex): 2E — read 13.6.6 ...
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Philips Semiconductors The HCD must take care of the difference that the internal buffer RAM is organized in bytes. The HCD must write the byte count into the HcTransferCounter register, but the HCD reads or writes the buffer RAM by ...
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Philips Semiconductors 1. Command phase: when address bit the DC interprets the data on the lower byte of the bus (bits command code. Commands without a data phase are executed immediately. 2. ...
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Philips Semiconductors Table 74: Command and register summary Name Read Endpoint n Buffer ( 14) Stall Control OUT Endpoint Stall Control IN Endpoint Stall Endpoint 14) Read Control OUT Status Read Control ...
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Philips Semiconductors Table 74: Command and register summary Name Read Chip ID Read Interrupt Register [1] With N representing the number of bytes, the number of words for 16-bit bus width is DIV 2. [2] Validating an ...
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Philips Semiconductors Table 76: Endpoint Configuration Register: bit description Bit 14.1.2 Write/Read Device Address This command is used to set the USB assigned address in the Address Register and enable the USB device. ...
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Philips Semiconductors Table 79: Mode Register: bit allocation Bit 7 6 Symbol DMAWD reserved [1] Reset 0 0 Access R/W R/W [1] Unchanged by a bus reset. Table 80: Mode Register: bit description Bit ...
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Philips Semiconductors Bit 7 6 Symbol DAKOLY DRQPOL Reset 0 1 Access R/W R/W Table 82: Hardware Configuration Register: bit description Bit 9397 750 08313 ...
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Philips Semiconductors 14.1.5 Write/Read Interrupt Enable Register This command is used to individually enable/disable interrupts from all endpoints, as well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend, resume, reset). A bus reset will ...
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Philips Semiconductors 14.1.6 Write/Read DMA Configuration This command defines the DMA configuration of ISP1161’s DC and enables/disables DMA transfers. The command accesses the DMA Configuration Register, which consists of 2 bytes. The bit allocation is given in DMAEN (DMA disabled), ...
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Philips Semiconductors 14.1.7 Write/Read DMA Counter This command accesses the DMA Counter Register. The bit allocation is given in Table the register returns the number of remaining bytes in the current transfer. A bus reset will not change the programmed ...
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Philips Semiconductors 14.2.1 Write/Read Endpoint Buffer This command is used to access endpoint FIFO buffers for reading or writing. First, the buffer pointer is reset to the beginning of the buffer. Following the command, a maximum ...
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Philips Semiconductors meaningful after a successful transaction. Exception: during DMA access of a double-buffered endpoint, the buffer pointer automatically points to the secondary buffer after reaching the end of the primary buffer. 14.2.2 Read Endpoint Status This command is used ...
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Philips Semiconductors 14.2.3 Stall Endpoint/Unstall Endpoint These commands are used to stall or unstall an endpoint. The commands modify the content of the Endpoint Status Register (see A stalled control endpoint is automatically unstalled when it receives a SETUP token, ...
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Philips Semiconductors Table 93: Endpoint Status Image Register: bit allocation Bit 7 6 Symbol EPSTAL EPFULL1 Reset 0 0 Access R R Table 94: Endpoint Status Image Register: bit description Bit 14.2.7 ...
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Philips Semiconductors Transaction — read 1 word Table 95: Error Code Register: bit allocation Bit 7 6 Symbol UNREAD DATA01 Reset 0 0 Access R R Table 96: Error Code Register: bit description Bit ...
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Philips Semiconductors After waking up from ‘suspend’ state, the firmware must unlock the registers and FIFOs via this command, by writing the unlock code (AA37H) into the Lock Register. The bit allocation of the Lock Register is given in Code ...
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Philips Semiconductors 14.3.4 Read Frame Number This command returns the frame number of the last successfully received SOF followed by reading one word from the Frame Number Register, containing the frame number. The Frame Number Register is shown ...
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Philips Semiconductors Table 105:Chip ID Register: bit description Bit 14.3.6 Read Interrupt Register This command indicates the sources of interrupts as stored in the 4-byte Interrupt Register. Each individual endpoint has its own interrupt ...
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Philips Semiconductors Table 107: Interrupt Register: bit description Bit 15. Reset Pin RESET is the hardware reset input of ISP1161 active LOW. To reset all internal logic, the minimum timing requirement is ...
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Philips Semiconductors ISP1161 1 USB upstream V reg(3.3) D_DP port connector V hold1 V hold2 Fig 41. Using supply. 17. External clock input The ISP1161 has a crystal oscillator designed for a 6 ...
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Philips Semiconductors 18. Limiting values Table 108:Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage to V CC(5V supply voltage to V CC(3.3V) reg(3.3) V input voltage I I ...
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Philips Semiconductors 19. Static characteristics Table 110:Static characteristics; supply pins V = 3 4 GND Symbol Parameter internal regulator output reg(3.3) I operating supply current ...
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Philips Semiconductors Table 112:Static characteristics: analog I/O pins ( 3 4 GND Symbol Parameter Input levels V differential input sensitivity DI V differential common mode CM ...
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Philips Semiconductors 20. Dynamic characteristics Table 113:Dynamic characteristics V = 3 4 GND Symbol Parameter Reset t pulse width on input RESET W(RESET) Crystal oscillator f crystal frequency XTAL [1] Dependent ...
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Philips Semiconductors 20.1 Timing symbols Table 115:Legend for timing characteristics Symbol Time symbols t T Signal names Logic levels ...
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Philips Semiconductors 20.2 Parallel I/O timing Table 116:Dynamic characteristics: parallel interface timing Symbol Parameter Read timing t first RD/WR after CMD SHSL t CS LOW to RD LOW SLRL t RD HIGH to CS HIGH RHSH t RD LOW pulse ...
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Philips Semiconductors 20.3 DMA interface timing 20.3.1 HC single-cycle burst mode DMA timing Table 117:Dynamic characteristics: HC single-cycle burst mode DMA timing Symbol Parameter Read/write timing t RD pulse width RL t read process data setup time RLDV t read ...
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Philips Semiconductors 20.3.2 HC multi-cycle burst mode DMA timing Table 118:Dynamic characteristics: HC multi-cycle burst mode DMA timing Symbol Parameter Read/write timing (for 4-cycle and 8-cycle burst mode) t WR/RD LOW pulse width RL t WR/RD HIGH to next WR/RD ...
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Philips Semiconductors 20.3.3 External EOT timing for HC single-cycle burst mode DMA Fig 48. External EOT timing for HC single-cycle burst mode DMA. 20.3.4 External EOT timing for HC multi-cycle burst mode DMA Fig 49. External EOT timing for HC ...
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Philips Semiconductors 20.3.6 DC single-cycle DMA timing (DACK-only mode) Table 120:Dynamic characteristics: DC single-cycle DMA timing (DACK-only mode) Symbol Parameter t DACK2 ON to DREQ2 OFF ALRL t DACK2 OFF to DREQ2 ON AHRH t DACK2 ON to data valid ...
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Philips Semiconductors 20.3.8 DC multi-cycle burst mode DMA timing Table 122:Dynamic characteristics: DC multi-cycle burst mode DMA timing Symbol Parameter t DREQ2 ON to first RD/WR OFF RHSH t last RD/ DREQ2 OFF SLRL t last RD/WR OFF ...
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Philips Semiconductors 21. Application information 21.1 Typical interface circuit 5 V 3.3 V SH7709 D [ 15 CS5 RD RD/WR DREQ0 DACK0 DREQ1 DACK1 5 V CLKOUT EXTAL IRQ2 IRQ3 PTC0 XTAL PTC1 ...
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Philips Semiconductors 21.2 Interfacing a ISP1161 with a SH7709 RISC processor This section shows a typical interface circuit between ISP1161 and a RISC processor. The Hitachi SH-3 series RISC processor SH7709 is used as the example. The main ISP1161 signals ...
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Philips Semiconductors the device stack. The device stack provides API directly to the application task for device function; the host stack provides API for Class driver and device driver, both of which provide API for application tasks for host function. ...
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Philips Semiconductors Load capacitance: Speed: Fig 57. Load impedance for D_DP and D_DM pins. 9397 750 08313 Product data Full-speed USB single-chip host and device controller 22 D.U. (full-speed mode). L full-speed mode only: internal 1.5 ...
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Philips Semiconductors 23. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the ...
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Philips Semiconductors LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A ...
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Philips Semiconductors 24. Soldering 24.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages ...
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Philips Semiconductors During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. ...
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Philips Semiconductors 26. Data sheet status [1] [2] Data sheet status Product status Objective data Development Preliminary data Qualification Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product ...
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Philips Semiconductors Philips Semiconductors - a worldwide company Argentina: see South America Australia: Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Tel. +43 160 101, Fax. +43 160 101 1210 Belarus: Tel. +375 17 220 0733, Fax. ...
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Philips Semiconductors Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . ...