CY7C1041BV33-25VC Cypress Semiconductor Corporation., CY7C1041BV33-25VC Datasheet

no-image

CY7C1041BV33-25VC

Manufacturer Part Number
CY7C1041BV33-25VC
Description
256K x 16 static RAM, 25ns
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Features
Cypress Semiconductor Corporation
Document Number: 38-05134 Rev. *I
Temperature ranges
Pin and function compatible with CY7C1041BV33
High speed
Low active power
2.0V data retention
Automatic power down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin
TSOP II and 48-Ball FBGA packages
Logic Block Diagram
Commercial: 0°C to 70°C
Industrial: –40°C to 85°C
Automotive-A: –40°C to 85°C
Automotive-E: –40°C to 125°C
t
t
324 mW (max)
AA
AA
= 10 ns (Commercial, Industrial and Automotive-A)
= 12 ns (Automotive-E)
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
198 Champion Court
COLUMN DECODER
INPUT BUFFER
RAM Array
256K x 16
Functional Description
The CY7C1041CV33 is a high performance CMOS static RAM
organized as 262,144 words by 16 bits.
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
specified on the address pins (A
Enable (BHE) is LOW, then data from IO pins (IO
is written into the location specified on the address pins (A
through A
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO
Byte High Enable (BHE) is LOW, then data from memory
appears on IO
Table
modes.
The input and output pins (IO
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
For best practice recommendations, refer to the Cypress
application note
on page 9 for a complete description of Read and Write
4-Mbit (256K x 16) Static RAM
17
San Jose
).
8
AN1064, SRAM System
to IO
0
through IO
,
15
CA 95134-1709
IO
IO
. For more information, see the
0
8
–IO
–IO
BHE
WE
OE
BLE
CE
0
7
15
through IO
7
), is written into the location
0
CY7C1041CV33
Revised February 14, 2008
through A
15
Guidelines.
) are placed in a high
17
). If Byte High
8
408-943-2600
through IO
0
to IO
Truth
7
15
. If
0
[+] Feedback
[+] Feedback
)

Related parts for CY7C1041BV33-25VC

CY7C1041BV33-25VC Summary of contents

Page 1

... Commercial: 0°C to 70°C ❐ Industrial: –40°C to 85°C ❐ Automotive-A: –40°C to 85°C ❐ Automotive-E: –40°C to 125°C ■ Pin and function compatible with CY7C1041BV33 ■ High speed ❐ (Commercial, Industrial and Automotive-A) AA ❐ (Automotive-E) AA ■ ...

Page 2

Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Pin Configuration Figure 1. 44-Pin SOJ/TSOP II (Top View ...

Page 3

Pin Definitions SOJ, TSOP BGA Pin Name Pin Number Pin Number A –A 1–5, 18–27, A3, A4, A5, B3 42–44 B4, C3, C4, D4, H2, H3, H4, H5, G3, G4, F3, F4, E4 –IO 7–10,13–16, B1, ...

Page 4

Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C [2] Supply Voltage on V Relative ...

Page 5

Capacitance Tested initially and after any design or process changes that may affect these parameters Parameter Description C Input Capacitance IN C Output Capacitance OUT Thermal Resistance Tested initially and after any design or process changes that may affect these ...

Page 6

Switching Characteristics [4] Over the Operating Range Parameter Description Read Cycle [ (Typical) to the First Access power CC t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t ...

Page 7

Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled) ADDRESS DATA OUT PREVIOUS DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) ADDRESS CE t ACE OE BHE, BLE t t LZBE HIGH IMPEDANCE DATA OUT t ...

Page 8

Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (CE Controlled) ADDRESS BHE, BLE DATA IO Figure 7. Write Cycle No. 2 (BLE or BHE Controlled) ADDRESS t SA BHE, BLE WE CE DATA IO Notes ...

Page 9

Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS BHE, BLE DATA IO Truth Table BLE BHE ...

Page 10

Ordering Information Speed Package Ordering Code (ns) Diagram 10 CY7C1041CV33-10BAXC 51-85106 48-ball Fine Pitch BGA (Pb-Free) CY7C1041CV33-10VC 51-85082 44-pin (400-mil) Molded SOJ CY7C1041CV33-10VXC CY7C1041CV33-10ZXC 51-85087 44-pin TSOP II (Pb-Free) CY7C1041CV33-10BAI 51-85106 48-ball Fine Pitch BGA CY7C1041CV33-10BAXI CY7C1041CV33-10ZI 51-85087 44-pin TSOP ...

Page 11

Package Diagrams Figure 9. 44-Pin (400 Mil) Molded SOJ, 51-85082 Document Number: 38-05134 Rev. *I CY7C1041CV33 51-85082-*B Page [+] Feedback [+] Feedback ...

Page 12

Package Diagrams (continued) Figure 10. 44-Pin Thin Small Outline Package Type II, 51-85087 Document Number: 38-05134 Rev. *I CY7C1041CV33 51-85087-*A Page [+] Feedback [+] Feedback ...

Page 13

Package Diagrams (continued) Figure 11. 48-Ball FBGA (7 x 8.5 x 1.2 mm), 51-85106 TOP VIEW A1 CORNER 7.00±0.10 SEATING PLANE C Document Number: ...

Page 14

Document History Page Document Title: CY7C1041CV33, 4-Mbit (256K x 16) Static RAM Document Number: 38-05134 Issue Orig. of REV. ECN NO. Date Change ** 109513 12/13/01 HGK *A 112440 12/20/01 BSS *B 112859 03/25/02 DFP *C 116477 09/16/02 CEA *D ...

Related keywords