CY7C4275-25ASC Cypress Semiconductor Corporation., CY7C4275-25ASC Datasheet
CY7C4275-25ASC
Related parts for CY7C4275-25ASC
CY7C4275-25ASC Summary of contents
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... FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and a read enable pin (REN). In addition, the CY7C4275/85 have an output enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications ...
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... Functional Description (continued) The CY7C4275/85 provides five status pins. These pins are decod determine one of five states: Empty, Almost Empty, Half Full, Almost Full, and Full (see Table 2). The Half Full flag shares the WXO pin ...
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... HIGH, the FIFO’s outputs are in High Z (high-impedance) state. I Dual-Mode Pin Asynchronous Almost Empty/Almost Full flags – tied to V Synchronous Almost Empty/Almost Full flags – tied to V (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) CY7C4275 CY7C4285 Function /SMODE is tied CC /SMODE is tied to V ...
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... V = Max. – > – < V < Com’l Ind Com’l Ind Test Conditions MHz 5.0V CC CY7C4275 CY7C4285 Ambient Temperature + – + 7C42X5-5 7C42X5-25 Max. Min. Max. Min. Max. 2.4 2.4 0.4 0.4 0.4 V 2 ...
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... OUTPUT 7C42X5-10 Description Min. 4.5 4.5 0.5 0.5 [12] [12] [13] /SMODE tied /SMODE tied [13] /SMODE tied OHZ . PAF(E) CY7C4275 CY7C4285 ALL INPUT PULSES 90% 90% 10% 10 410 1.91V 7C42X5-15 7C42X5-25 Max. Min. Max. Min. 100 66 ...
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... Skew Time between Read Clock and Write Clock for SKEW3 Programmable Almost Empty and Programmable Al- most Full Flags (Synchronous Mode only) Document #: 38-06008 Rev. *A 7C42X5-10 Description Min. /SMODE tied 4.5 CY7C4275 CY7C4285 7C42X5-15 7C42X5-25 Max. Min. Max. Min ...
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... NO OPERATION t REF [15] t SKEW2 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4275 CY7C4285 ENH NO OPERATION t WFF t REF VALID DATA t OHZ 4275–6 4275– ...
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... Document #: 38-06008 Rev RSF t RSF t RSF D 1 [18] t FRL t SKEW2 t REF t OLZ t OE (maximum When t < minimum specification, t CLK SKEW2 SKEW2 CY7C4275 CY7C4285 t RSR [17] OE=1 OE [19 (maximum) = either 2 FRL CLK SKEW2 4275– 4275– ...
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... REN LOW OE DATA IN OUTPUT REGISTER Q – Document #: 38-06008 Rev. *A [18 REF REF DATA WRITE t WFF t ENH t A DATA READ CY7C4275 CY7C4285 ENH ENS [18] t FRL t t SKEW2 D0 NO WRITE [14] t SKEW1 t t WFF WFF t ENH ...
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... Document #: 38-06008 Rev CLKL CLKH t t ENS ENH CLKL CLKH t t ENS ENH t PAE CY7C4275 CY7C4285 HALF FULL + 1 OR MORE HALF FULLOR LESS ENS WORDS n WORDS IN FIFO IN FIFO t PAE t ENS 4275–12 4275–13 Page ...
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... If a read is preformed on this rising edge of the read clock, there will be Empty + (n 1) words in the FIFO when PAE goes LOW. 24. PAF offset = m. Number of data words written into FIFO already = 32768 25. PAF is offset = m. 26. 32768 m words in CY7C4275 and 65536 – m words in CY7C4285. 27. 32768 ( words in CY7C4275 and 65536 – CY7C4285. ...
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... Note ENS ENH Note 29 t PAF IN FIFO t CLKL t ENH t DH PAE OFFSET PAF OFFSET (m 1) words of the FIFO when PAF goes LOW. CY7C4275 CY7C4285 FULL– M WORDS [26] IN FIFO t [30] PAF synch t SKEW3 ENS ENS ENH PAE OFFSET – D ...
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... Read from last physical location. Document #: 38-06008 Rev CLKL t ENH t A UNKNOWN PAE OFFSET t CLKH Note Note CLKH Note XIS CY7C4275 CY7C4285 PAF OFFSET PAE OFFSET 4275–18 4275–19 4275–20 4275–21 Page ...
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... The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t 35. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t Document #: 38-06008 Rev XIS t PRT t RTR RTR to update these flags. RTR CY7C4275 CY7C4285 4275–22 4275–23 . Page ...
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... Architecture The CY7C4275/85 consists of an array of 32K/64K words of 18 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C4275/85 also includes the control signals WXI, RXI, WXO, RXO for depth expansion ...
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... Notes: 37 Empty Offset (Default Values: CY7C4275/CY7C4285 n = 127). 38 Full Offset (Default Values: CY7C4275/CY7C4285 n = 127). Document #: 38-06008 Rev. *A nal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and t after the retransmit pulse ...
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... Width Expansion Configuration The CY7C4275/85 can be expanded in width to provide word widths greater than 18 in increments of 18. During width ex- pansion mode all control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing RESET (RS) DATA IN ( ...
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... Depth Expansion Configuration (with Programmable Flags) The CY7C4275/85 can easily be adapted to applications re- quiring more than 32,768/65,536 words of buffering. Figure 2 shows Depth Expansion using three CY7C42X5s. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input ...
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... Package Package Name Type A64 64-Lead 10x10 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack CY7C4275 CY7C4285 Operating Range Commercial Industrial Commercial Commercial Operating Range Commercial Industrial Commercial ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C4275 CY7C4285 ...
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... Document Title: CY7C4275, CY7C4285 32K/64K X 18 Deep Sync FIFOs Document Number: 38-06008 Issue REV. ECN NO. Date ** 106469 07/12/01 *A 122260 12/26/02 Document #: 38-06008 Rev. *A Orig. of Change SZV Change from Spec Number: 38-00588 to 38-06008 RBI Power up requirements added to Maximum Ratings Information CY7C4275 CY7C4285 Description of Change ...