MPC9773 Freescale Semiconductor, Inc, MPC9773 Datasheet

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MPC9773

Manufacturer Part Number
MPC9773
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2005. All rights reserved.
3.3 V 1:12 LVCMOS PLL Clock
Generator
for high-performance low-skew clock distribution in mid-range to high-
performance networking, computing, and telecom applications. With output
frequencies up to 240 MHz and output skews less than 250 ps the device meets
the needs of the most demanding clock applications.
Features
Functional Description
MPC9773 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The
reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match
the VCO frequency range. The MPC9773 features an extensive level of frequency programmability between the 12 outputs as
well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3.
feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference
versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addi-
tion, the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-
binary factor. The MPC9773 also supports the 180° phase shift of one of its output banks with respect to the other output banks.
The QSYNC outputs reflect the phase relationship between the QA and QC outputs and can be used for the generation of system
baseline timing signals.
LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass con-
figuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers,
bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics
do not apply.
MPC9773. The MPC9773 has an internal power-on reset.
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission
lines. For series terminated transmission lines, each of the MPC9773 outputs can drive one or two traces, giving the devices an
effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package.
The MPC9773 is a 3.3 V compatible, 1:12 PLL based clock generator targeted
The MPC9773 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the
The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative
The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the
The MPC9773 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except PCLK) accept
down support
52-lead Pb-free package available
1:12 PLL based low-voltage clock generator
3.3 V power supply
Internal power-on reset
Generates clock signals up to 242.5 MHz
Maximum output skew of 250 ps
Differential PECL reference clock input
Two LVCMOS PLL reference clock inputs
External PLL feedback supports zero-delay capability
Various feedback and output dividers (refer to Application Section)
Supports up to three individual generated output clock frequencies
Synchronous output clock stop circuitry for each individual output for power
Drives up to 24 clock lines
Ambient temperature range -40°C to +85°C
Pin and function compatible to the MPC973
PLL CLOCK GENERATOR
52-LEAD LQFP PACKAGE
52-LEAD LQFP PACKAGE
3.3 V 1:12 LVCMOS
Pb-FREE PACKAGE
MPC9773
CASE 848D-03
CASE 848D-03
FA SUFFIX
AE SUFFIX
Rev 5, 08/2005
MPC9773

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MPC9773 Summary of contents

Page 1

... The MPC9773 also supports the 180° phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflect the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals ...

Page 2

... FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 V CC QA2 GND QA1 V CC QA0 GND VCO_SEL Figure 2. MPC9773 52-Lead Package Pinout (Top View) MPC9773 2 Ω 0 ÷4, ÷6, ÷8, ÷12 ÷2 0 VCO ÷4, ÷6, ÷8, ÷ ÷1 ÷2, ÷4, ÷6, ÷8 PLL ÷4, ÷6, ÷8, ÷10 ÷ ...

Page 3

... Outputs disabled (high-impedance state) and device is reset. During reset/ output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC9773 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. ...

Page 4

... MPC9773 4 Table 5. Ouput Divider Bank C (N QA[0:3] VCO_SEL FSEL_C1 VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ 12 ...

Page 5

... CMR and the input swing lies within the The MPC9773 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage Inputs have pull-down resistors affecting the input current. Advanced Clock Drivers Device Data ...

Page 6

... Output Disable Time PLZ Output Enable Time PZL, LZ (9) t Cycle-to-cycle Jitter JIT(CC) (10) t Period Jitter JIT(PER) I/O Phase Jitter RMS (1 σ) t JIT(∅) MPC9773 6 (1), (2) = -40°C to 85°C) A Min ÷ 4 feedback 50.0 ÷ 6 feedback 33.3 ÷ 8 feedback 25.0 ÷ 10 feedback 20.0 ÷ 12 feedback 16.6 ÷ ...

Page 7

... Normal AC operation is obtained when the crosspoint is within the V CMR and the input swing lies within the Calculation of reference duty cycle limits The MPC9773 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t be guaranteed are within the specified range ...

Page 8

... MPC9773 Configurations Configuring the MPC9773 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: ⋅ M ÷ OUT REF f ÷VCO_SEL PLL REF ÷M where f is the reference frequency of the selected input REF clock source (CCLKO, CCLK1 or PCLK the PLL feedback divider and output divider ...

Page 9

... STOP_DATA input by supplying a logic ‘0’ start bit followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the free-running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the MPC9773 can sample each STOP_DATA bit with the rising edge of the free-running STOP_CLK signal. (See QA1 ...

Page 10

... QSYNC. In configurations for which the output frequency relationships are not integer multiples of each other, QSYNC provides a signal for system synchronization purposes. The MPC9773 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic low) one period in duration and one period prior to the ...

Page 11

... CMOS fanout buffers. The external feedback option of the ) and the MPC9773 clock driver allows for its use as a zero delay CC buffer. The PLL aligns the feedback clock output edge with the clock input reference edge, resulting in a near zero delay through the device (the propagation delay through the device is virtually eliminated) ...

Page 12

... Driving Transmission Lines The MPC9773 clock driver was designed to drive high PD, LINE(FB) speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 Ω, the drivers can drive either parallel or series terminated transmission lines ...

Page 13

... This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9773 clock driver. For the series terminated case, however, there current draw; thus the outputs can drive multiple series terminated lines. ...

Page 14

... MPC9773 DUT = 50 Ω Ω Figure 15. CCLK MPC9773 AC Test Reference MPC9773 DUT = 50 Ω Ω Figure 16. PCLK MPC9773 AC Test Reference = 50 Ω Ω Ω Ω Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 15

... V CC GND GND t (∅) , Static Phase (∅) Offset) Test Reference mean| JIT(∅ for a controlled edge with respect mean in a random 0 0 Figure 20. I/O Jitter –1/f | JIT(PER Figure 22. Period Jitter MPC9773 ÷ 2 ÷ ...

Page 16

... MPC9773 16 PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE PAGE Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 17

... Advanced Clock Drivers Device Data Freescale Semiconductor PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE PAGE MPC9773 17 ...

Page 18

... MPC9773 18 PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE PAGE Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 19

... Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com MPC9773 Rev. 5 08/2005 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...

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