MPC9773 Freescale Semiconductor, Inc, MPC9773 Datasheet
MPC9773
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MPC9773 Summary of contents
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... The MPC9773 also supports the 180° phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflect the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals ...
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... FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 V CC QA2 GND QA1 V CC QA0 GND VCO_SEL Figure 2. MPC9773 52-Lead Package Pinout (Top View) MPC9773 2 Ω 0 ÷4, ÷6, ÷8, ÷12 ÷2 0 VCO ÷4, ÷6, ÷8, ÷ ÷1 ÷2, ÷4, ÷6, ÷8 PLL ÷4, ÷6, ÷8, ÷10 ÷ ...
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... Outputs disabled (high-impedance state) and device is reset. During reset/ output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC9773 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. ...
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... MPC9773 4 Table 5. Ouput Divider Bank C (N QA[0:3] VCO_SEL FSEL_C1 VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ VCO ÷ 12 ...
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... CMR and the input swing lies within the The MPC9773 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage Inputs have pull-down resistors affecting the input current. Advanced Clock Drivers Device Data ...
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... Output Disable Time PLZ Output Enable Time PZL, LZ (9) t Cycle-to-cycle Jitter JIT(CC) (10) t Period Jitter JIT(PER) I/O Phase Jitter RMS (1 σ) t JIT(∅) MPC9773 6 (1), (2) = -40°C to 85°C) A Min ÷ 4 feedback 50.0 ÷ 6 feedback 33.3 ÷ 8 feedback 25.0 ÷ 10 feedback 20.0 ÷ 12 feedback 16.6 ÷ ...
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... Normal AC operation is obtained when the crosspoint is within the V CMR and the input swing lies within the Calculation of reference duty cycle limits The MPC9773 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t be guaranteed are within the specified range ...
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... MPC9773 Configurations Configuring the MPC9773 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: ⋅ M ÷ OUT REF f ÷VCO_SEL PLL REF ÷M where f is the reference frequency of the selected input REF clock source (CCLKO, CCLK1 or PCLK the PLL feedback divider and output divider ...
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... STOP_DATA input by supplying a logic ‘0’ start bit followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the free-running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the MPC9773 can sample each STOP_DATA bit with the rising edge of the free-running STOP_CLK signal. (See QA1 ...
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... QSYNC. In configurations for which the output frequency relationships are not integer multiples of each other, QSYNC provides a signal for system synchronization purposes. The MPC9773 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic low) one period in duration and one period prior to the ...
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... CMOS fanout buffers. The external feedback option of the ) and the MPC9773 clock driver allows for its use as a zero delay CC buffer. The PLL aligns the feedback clock output edge with the clock input reference edge, resulting in a near zero delay through the device (the propagation delay through the device is virtually eliminated) ...
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... Driving Transmission Lines The MPC9773 clock driver was designed to drive high PD, LINE(FB) speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 Ω, the drivers can drive either parallel or series terminated transmission lines ...
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... This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9773 clock driver. For the series terminated case, however, there current draw; thus the outputs can drive multiple series terminated lines. ...
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... MPC9773 DUT = 50 Ω Ω Figure 15. CCLK MPC9773 AC Test Reference MPC9773 DUT = 50 Ω Ω Figure 16. PCLK MPC9773 AC Test Reference = 50 Ω Ω Ω Ω Advanced Clock Drivers Device Data Freescale Semiconductor ...
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... V CC GND GND t (∅) , Static Phase (∅) Offset) Test Reference mean| JIT(∅ for a controlled edge with respect mean in a random 0 0 Figure 20. I/O Jitter –1/f | JIT(PER Figure 22. Period Jitter MPC9773 ÷ 2 ÷ ...
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... MPC9773 16 PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE PAGE Advanced Clock Drivers Device Data Freescale Semiconductor ...
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... Advanced Clock Drivers Device Data Freescale Semiconductor PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE PAGE MPC9773 17 ...
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... MPC9773 18 PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE PAGE Advanced Clock Drivers Device Data Freescale Semiconductor ...
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... Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com MPC9773 Rev. 5 08/2005 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...