SY100ELT23ZCTR

Manufacturer Part NumberSY100ELT23ZCTR
ManufacturerMicrel Semiconductor
SY100ELT23ZCTR datasheet
 
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Micrel
FEATURES
3.0ns typical propagation delay
<500ps typical output-to-output skew
Differential PECL inputs
24mA TTL outputs
Flow-through pinouts
Internal input 50k pulldown resistors
Available in 8-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
D
1
0
D
2
0
PECL
TTL
D
3
1
D
4
1
SOIC
TOP VIEW
Precision Edge is a registered trademark of Micrel, Inc.
DUAL DIFFERENTIAL
PECL-to-TTL
TRANSLATOR
DESCRIPTION
The SY10/100ELT23 are dual differential PECL-to-TTL
translators. Because PECL (Positive ECL) levels are
used, only +5V and ground are required. The small outline
8-lead SOIC package and the low skew dual gate design
of the ELT23 makes it ideal for applications which require
the translation of a clock and a data signal.
The ELT23 is available in both ECL standards: the
10ELT is compatible with positive ECL 10H logic levels,
while the 100ELT is compatible with positive ECL 100K
logic levels.
8
V
CC
PIN NAMES
7
Q
0
Pin
6
Q
1
Q
n
5
GND
D
n
V
CC
GND
1
Precision Edge
SY10ELT23
Precision Edge
®
SY100ELT23
SY10ELT23
SY100ELT23
®
Precision Edge
Function
TTL Outputs
Differential PECL Inputs
+5.0V Supply
Ground
Rev.: J
Amendment: 0
Issue Date: February 2008
®

SY100ELT23ZCTR Summary of contents