BH616UV8010TIG55 Brilliance Semiconductor, Inc., BH616UV8010TIG55 Datasheet

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BH616UV8010TIG55

Manufacturer Part Number
BH616UV8010TIG55
Description
Manufacturer
Brilliance Semiconductor, Inc.
Datasheet

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BH616UV8010TIG55
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BH616UV8010TIG55
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BI
Quantity:
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n FEATURES
Ÿ Wide V
Ÿ Ultra low power consumption :
Ÿ High speed access time :
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE1, CE2 and OE options
Ÿ I/O Configuration x8/x16 selectable by LB and UB pin.
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation, no clock, no refresh
Ÿ Data retention supply voltage as low as 1.0V
n POWER CONSUMPTION
n PIN CONFIGURATIONS
R0201-BH616UV8010
CE2
A15
A14
A13
A12
A10
A18
A17
A11
WE
Brilliance Semiconductor, Inc.
Detailed product characteristic test report is available upon request and being accepted.
NC
NC
NC
UB
V
V
-55
-70
BH616UV8010DI
BH616UV8010AI
BH616UV8010TI
A9
A8
LB
A7
A6
A5
A4
A3
A2
A1
CC
CC
PRODUCT
= 3.6V
= 1.2V
FAMILY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CC
low operation voltage : 1.65V ~ 3.6V
G
A
B
C
D
E
F
H
DQ14
DQ15
DQ8
DQ9
VSS
VCC
A18
Operation current : 12mA (Max.) at 55ns
Standby current : 2.5uA (Typ.) at 3.0V/25
Data retention current : 1.2uA (Typ.) at 25
55ns (Max.) at V
70ns (Max.) at V
LB
1
TEMPERATURE
DQ10
DQ11
DQ12
DQ13
OE
UB
NC
A8
BH616UV8010TI
-40
2
48-ball BGA top view
OPERATING
Industrial
O
VSS
C to +85
A17
A14
A12
A0
A3
A5
A9
3
Pb-Free and Green package materials are compliant to RoHS
Ultra Low Power/High Speed CMOS SRAM
512K X 16 bit
A16
A15
A13
A10
A1
A4
A6
A7
4
CC
CC
=1.65~3.6V
=1.65~3.6V
O
C
2mA (Max.) at 1MHz
CE1
DQ1
DQ3
DQ4
DQ5
A11
WE
A2
5
V
VCC
CE2
DQ0
DQ2
VSS
DQ6
DQ7
CC
15uA
NC
6
=3.6V
STANDBY
(I
CCSB1
reserves the right to change products and specifications without notice.
, Max)
V
CC
12uA
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
=1.8V
O
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE1
A0
O
C
C
1MHz
2mA
1
POWER DISSIPATION
n DESCRIPTION
The BH616UV8010 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 524,288 by 16 bits and
operates in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical operating current of
1.5mA at 1MHz at 3.6V/25
1.65V/85
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH616UV8010 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BH616UV8010 is available in DICE form, JEDEC standard
48-pin TSOP-I and 48-ball BGA package.
n BLOCK DIAGRAM
V
10MHz
CC
DQ15
6mA
DQ0
CE2
CE1
A12
A11
A10
WE
=3.6V
V
OE
UB
V
A9
A8
A7
A6
A5
A4
A3
LB
.
.
.
.
.
.
CC
SS
O
C.
.
.
.
.
.
.
12mA
Address
Buffer
Input
f
Max.
Operating
Control
(I
16
16
CC
, Max)
10
1.5mA
1MHz
O
Output
C and maximum access time of 55ns at
Buffer
Buffer
Data
Input
Data
Decoder
Row
V
10MHz
BH616UV8010
CC
5mA
16
=1.8V
16
1024
A18
8mA
f
A17
Max.
Address Input Buffer
A15
Column Decoder
Memory Array
1024 x 8192
Write Driver
Revision
May.
Column I/O
Sense Amp
A14
DICE
BGA-48-0608
TSOP I-48
PKG TYPE
A13
512
9
8192
A16 A2 A1
2006
1.2
A0

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BH616UV8010TIG55 Summary of contents

Page 1

... A8 A9 A10 A11 48-ball BGA top view Brilliance Semiconductor, Inc. Detailed product characteristic test report is available upon request and being accepted. R0201-BH616UV8010 n DESCRIPTION The BH616UV8010 is a high performance, ultra low power CMOS Static Random Access Memory organized as 524,288 by 16 bits and operates in a wide range of 1 ...

Page 2

PIN DESCRIPTIONS Name A0-A18 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input WE Write Enable Input OE Output Enable Input LB and UB Data Byte Control Input DQ0-DQ15 Data Input/Output Ports ...

Page 3

ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER Terminal Voltage with V TERM Respect to GND Temperature Under T BIAS Bias T Storage Temperature STG P Power Dissipation Output Current OUT 1. Stresses greater than those listed under ABSOLUTE ...

Page 4

DATA RETENTION CHARACTERISTICS (T SYMBOL PARAMETER V V for Data Retention Data Retention Current CCDR Chip Deselect to Data t CDR Retention Time t Operation Recovery Time R 1. Typical characteristics are at T =25 A ...

Page 5

AC ELECTRICAL CHARACTERISTICS (T READ CYCLE JEDEC PARANETER PARAMETER NAME NAME t t Read Cycle Time AVAX Address Access Time AVQX AA Chip Select Access Time t t E1LQV ACS1 t t Chip Select Access Time ...

Page 6

READ CYCLE 2 CE1 CE2 D OUT (1, 4) READ CYCLE 3 ADDRESS OE CE1 CE2 LB OUT NOTES high in read Cycle. 2. Device is continuously selected when CE1 = V 3. Address ...

Page 7

AC ELECTRICAL CHARACTERISTICS (T WRITE CYCLE JEDEC PARANETER PARAMETER NAME NAME t t Write Cycle Time AVAX Address Set up Time AVWL Address Valid to End of Write AVWH Chip ...

Page 8

WRITE CYCLE 2 ADDRESS CE1 CE2 LB OUT D IN NOTES must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 ...

Page 9

ORDERING INFORMATION BH616UV8010 Note: Brilliance Semiconductor Inc. (BSI) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which ...

Page 10

PACKAGE DIMENSIONS TSOP I-48 Pin (12mm x 20mm) R0201-BH616UV8010 BH616UV8010 10 Revision 1.2 May. 2006 ...

Page 11

Revision History Revision No. History 1.0 Initial Production Version 1.1 To improve access speed - from 70ns to 55ns 1.2 Change I-grade operation temperature range - from –25 O R0201-BH616UV8010 C to – BH616UV8010 Draft Date ...

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