PM5351-BI PMC-Sierra Inc, PM5351-BI Datasheet
PM5351-BI
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PM5351-BI Summary of contents
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... S/UNI 155 TETRA USER NETWORK INTERFACE PMC-Sierra, Inc. ISSUE 8 PM5351 S / ® SATURN (155 TETRA) DATA SHEET ISSUE 8: NOVEMBER 2005 100-2700 Production Way, Burnaby, BC Canada V5A 4X1 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 604.415.6000 ...
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... Updated ordering information including RoHS-compliant device details. • Converted Bit 0 of register 0x0E to “Reserved" • Added PERFCTRL register bit to register 0x0F • Changed AVGPER bit description in register 0xDD. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 100-2700 Production Way, Burnaby, BC Canada V5A 4X1 604.415.6000 ...
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... AIS condition Water Mark is 0xF0 100-2700 Production Way, Burnaby, BC Canada V5A 4X1 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 604.415.6000 ...
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... Page 313 – Updated DC characteristic • Page 336 – Updated air flow info PMC-Sierra, Inc. ISSUE 8 Water Mark to avoid FIFO overrruns Timing Diagram 100-2700 Production Way, Burnaby, BC Canada V5A 4X1 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 604.415.6000 ...
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... POWER AND GROUND .................................................................................... 49 10 FUNCTIONAL DESCRIPTION........................................................................................ 55 10.1 RECEIVE LINE INTERFACE (CRSI) ................................................................. 55 10.1.1 10.1.2 10.2 RECEIVE SECTION OVERHEAD PROCESSOR (RSOP) ............................... 56 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 CLOCK RECOVERY ...................................................................... 55 SERIAL TO PARALLEL CONVERTER .......................................... 56 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) i ...
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... BIT ERROR RATE MONITOR........................................................ 60 SYNCHRONIZATION STATUS EXTRACTION.............................. 61 POINTER INTERPRETER ............................................................. 61 SPE TIMING................................................................................... 65 ERROR MONITOR......................................................................... 65 CELL DELINEATION ...................................................................... 66 DESCRAMBLER ............................................................................ 68 CELL FILTER AND HCS VERIFICATION ...................................... 68 PERFORMANCE MONITOR.......................................................... 69 OVERHEAD REMOVAL ................................................................. 70 DESCRAMBLER ............................................................................ 70 POS FRAME DELINEATION ......................................................... 70 BYTE DESTUFFING ...................................................................... 71 FCS CHECK................................................................................... 71 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) ii ...
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... LINE BIP CALCULATE................................................................... 76 LINE RDI INSERT .......................................................................... 76 LINE FEBE INSERT ....................................................................... 76 POINTER GENERATOR ................................................................ 77 BIP-8 CALCULATE......................................................................... 78 FEBE CALCULATE ........................................................................ 78 IDLE/UNASSIGNED CELL GENERATOR ..................................... 78 SCRAMBLER ................................................................................. 78 HCS GENERATOR ........................................................................ 79 TRANSMIT FIFO ............................................................................ 79 POS FRAME GENERATOR........................................................... 80 FCS GENERATOR......................................................................... 80 BYTE STUFFING ........................................................................... 81 DATA SCRAMBLING...................................................................... 81 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) iii ...
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... PREMATURE RPA ASSERTION....................................... 86 TRANSMIT ATM INTERFACE........................................................ 87 TRANSMIT POS INTERFACE ....................................................... 88 PHASE COMPARISON .................................................................. 89 10.16.1.1 PHASE REACQUISITION CONTROL .............................. 90 PHASE AVERAGER....................................................................... 91 BOUNDARY SCAN CELLS.......................................................... 318 ATM MAPPING............................................................................. 321 PACKET OVER SONET/SDH MAPPING .................................... 322 TRANSPORT AND PATH OVERHEAD BYTES........................... 323 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) iv ...
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... LINE AND SECTION DCC TIMING ................................................................. 380 18.6 TRANSMIT AND RECEIVE FRAME PULSES ................................................ 382 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 TAP CONTROLLER ..................................................................... 336 13.7.1.1 STATES ............................................................................. 338 13.7.1.2 INSTRUCTIONS................................................................ 339 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) v ...
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... TRANSMIT LINE TIMING IN SINCLE ENDED TXD/TXC MODE ................... 383 18.8 JTAG TEST PORT TIMING.............................................................................. 383 19 ORDERING AND THERMAL INFORMATION .............................................................. 386 20 MECHANICAL INFORMATION..................................................................................... 388 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) vi ...
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... REGISTER 0X1D: RLOP LINE FEBE LSB................................................................................ 139 REGISTER 0X1E: RLOP LINE FEBE........................................................................................ 139 REGISTER 0X1F: RLOP LINE FEBE MSB ............................................................................... 140 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) vii ...
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... REGISTER 0X41: TPOP POINTER CONTROL........................................................................ 180 REGISTER 0X43: TPOP CURRENT POINTER LSB ................................................................ 183 REGISTER 0X44: TPOP CURRENT POINTER MSB ............................................................... 184 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) viii ...
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... REGISTER 0X70: RXCP_50 IDLE CELL COUNTER (MSB) ................................................... 223 REGISTER 0X80: TXCP_50 CONFIGURATION 1................................................................... 224 REGISTER 0X81: TXCP_50 CONFIGURATION 2................................................................... 226 REGISTER 0X82: TXCP_50 CELL COUNT STATUS/CONFIGURATION OPTIONS.............. 228 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) ix ...
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... REGISTER 0XAD: RXFP RECEIVE FRAME COUNTER ......................................................... 261 REGISTER 0XAE: RXFP RECEIVE FRAME COUNTER (MSB) .............................................. 261 REGISTER 0XAF: RXFP RECEIVE ABORTED FRAME COUNTER (LSB) ............................. 263 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) x ...
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... REGISTER 0XD4: WANS PHASE WORD [23:16] ................................................................... 283 REGISTER 0XD5: WANS PHASE WORD [30:24] ................................................................... 284 REGISTER 0XD9: WANS REFERENCE PERIOD [7:0]........................................................... 285 REGISTER 0XDA: WANS REFERENCE PERIOD [15:8] ........................................................ 285 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) xi ...
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... REGISTER 0XF5: RASE RECEIVE K1 ..................................................................................... 304 REGISTER 0XF6: RASE RECEIVE K2 ..................................................................................... 305 REGISTER 0XF7: RASE RECEIVE Z1/S1................................................................................ 306 REGISTER 0X400: MASTER TEST .......................................................................................... 308 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) xii ...
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... FIGURE 27: BOUNDARY SCAN ARCHITECTURE ................................................................. 335 FIGURE 28: TAP CONTROLLER FINITE STATE MACHINE ................................................... 337 FIGURE 29: WAN MODE ANALOG POWER PIN PASSIVE-FILTERING WITH 3.3V SUPPLY342 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) xiii ...
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... FIGURE 51: LINE SIDE TRANSMIT TIMING DIAGRAM (TXC_OE=1) ................................... 383 FIGURE 52: JTAG PORT INTERFACE TIMING....................................................................... 384 FIGURE 53:- MECHANICAL DRAWING 304 PIN SUPER BALL GRID ARRAY (SBGA).......... 388 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) xiv ...
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... TABLE 28: SECTION DCC TIMING (FIGURE 48) ................................................................... 380 TABLE 29: LINE DCC TIMING (FIGURE 49) ........................................................................... 381 TABLE 30: TRANSMIT AND RECEIVE FRAME PULSE TIMING (FIGURE 50) ...................... 382 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) xv ...
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... TABLE 31: LINE SIDE TRANSMIT TIMIGN (TXC_OE=1 ONLY) (FIGURE 51)...................... 383 TABLE 32: JTAG PORT INTERFACE (FIGURE 52)................................................................. 383 TABLE 33: ORDERING INFORMATION .................................................................................. 386 TABLE 34: THERMAL INFORMATION ...................................................................................... 386 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) xvi ...
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... Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes. • Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 1 ...
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... Interprets the received payload pointer (H1, H2) and extracts the STS-3c (STM-1) synchronous payload envelope and path overhead. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 2 ...
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... Checks for octet aligned packet lengths and for minimum and maximum packet lengths. Automatically deletes short packets (software configurable), and marks those exceeding the maximum length as errored. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA ...
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... Inserts ATM cells or POS frames into the transmitted STS-3c (STM-1) synchronous payload envelope. 1.6 The Transmit ATM Processor • Provides idle/unassigned cell insertion. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 4 ...
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... Aborts packets under the direction of the host or when the FIFO underflows. • Provides a synchronous 256 byte FIFO buffer accessed through the16-bit data bus on the POS-PHY System Interface. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA polynomial). 5 ...
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... LAN switches and hubs. • Packet switches and hubs. • Layer 3 switches. • Multiservice switches (FR, ATM, IP, etc..). • Gigabit and Terabit routers. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 6 ...
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... PMC-971147 “Saturn Compliant Interface for Packet over SONET Physical Layer and Link Layer Devices, Level 2”, Issue 3, February 1998. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 7 ...
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... S/UNI-TETRA DATASHEET PMC-1971240 • PMC-950820 “SONET/SDH Bit Error Threshold Monitoring Application Note”, Issue 2, September 1998. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 8 ...
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... Generic Flow Control HCS Header Check Sequence HDLC High-level Data Link Layer LAN Local Area Network LCD Loss of Cell Delineation PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 9 ...
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... Super Ball Grid Array SD Signal Degrade SDH Synchronous Digital Hierarchy SF Signal Fail SOH Section Overhead SONET Synchronous Optical Network PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 10 ...
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... Virtual Connection Indicator VCXO Voltage Controlled Oscillator VPI Virtual Path Indicator WAN Wide Area Network XOR Exclusive OR logic operator PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 11 ...
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... DATASHEET PMC-1971240 5 APPLICATION EXAMPLES The PM5351 S/UNI-TETRA is intended for use in equipment implementing Asynchronous Transfer Mode (ATM) User-Network Interfaces (UNI), ATM Network-Network Interfaces (NNI), as well as Packet over SONET/SDH (POS) interfaces. The POS interface can be used to support several packet based protocols, including the Point-to-Point Protocol (PPP). The S/UNI-TETRA may find application at either end of switch-to-switch links or switch-to-terminal links, both in public network (WAN) and private network (LAN) situations ...
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... Interface PM5351 S/UNI-155-TETRA TFCLK TENB TADR[4:0] TCA TSOC TPRTY TDAT[15:0] RFCLK RENB RADR[4:0] RCA RSOC RPRTY RDAT[15:0] PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) RXD1+/- Optical SD1 Transceiver TXD1+/- RXD2+/- Optical SD2 Transceiver TXD2+/- RXD3+/- Optical SD3 Transceiver TXD3+/- ...
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... TSOP TPRTY TDAT[15:0] TMOD TEOP TERR RFCLK RENB RADR[4:0] DRPA[4:1] RVAL RSOP RPRTY RDAT[15:0] RMOD REOP RERR PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) RXD1+/- Optical SD1 Transceiver TXD1+/- RXD2+/- Optical SD2 Transceiver TXD2+/- RXD3+/- Optical SD3 Transceiver TXD3+/- ...
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... TLDCLK1-4 TLD1-4 TSDCLK1-4 TSD1-4 TCLK TFPO TFPI PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Utopia / POS-PHY System Interface PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) INTB RSTB RDB W RB CSB ALE A[10:0] D[7:0] RLDCLK1-4 RLD1-4 ...
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... DATASHEET PMC-1971240 7 DESCRIPTION The PM5351 S/UNI-TETRA SATURN User Network Interface is a monolithic integrated circuit that implements four channel SONET/SDH processing, ATM mapping and Packet over SONET/SDH mapping functions at the STS-3c (STM- 1) 155.52 Mbit/s rate. The S/UNI-TETRA receives SONET/SDH streams using a bit serial interface, recovers the clock and data and processes section, line, and path overhead ...
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... The S/UNI-TETRA is implemented in low power, +3.3 Volt, CMOS technology. It has TTL and pseudo-ECL (PECL) compatible inputs and TTL/CMOS compatible outputs and is packaged in a 304 pin SBGA package. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 17 ...
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... RFPO1 TLDCLK4 TSDCLK4 RLD2 RALRM4 RCLK4 RFPO4 RFPO2 TFPO TLDCLK1 TSDCLK1 VSS RALRM2 RCLK3 RFPO3 VSS TCLK TLDCLK2 TSDCLK3 BOTTOM VIEW PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA TDO VSS N/C VSS N/C RAVD1_B RAVS1_B VSS TMS TCK ...
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... Please refer to the Operation section for a W1 discussion of PECL interfacing issues and for the V2 PECL voltage level selection through PECLV for 5V AA1 ODL interface. Y2 This pin is available independently for each channel. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 19 ...
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... AB13 receive line clock. RFPO pulses high for one RCLK cycle every 2430 RCLK cycles (STS-3c (STM-1)). RFPO is updated on the rising edge of RCLK. This pin is available independently for each channel. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 20 ...
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... R3 consumption and will likely require airflow. Most U4 optic modules don’t require TXC+/-. V3 TXD+/- is updated on the falling edge of TXC+/-. This pin is available independently for each channel. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 21 ...
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... MHz. TFPI is sampled on the rising edge of TCLK. TCLK does not apply to internally loop-timed channels, in which case the channel’s RCLK provides transmit timing information. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 22 ...
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... This pin is available independently for each channel. AB6 The transmit section DCC (TSD) signal contains the AA7 section data communications channel (D1-D3). Y8 TSD is sampled on the rising edge of TSDCLK. AB7 This pin is available independently for each channel. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 23 ...
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... The transmit line DCC clock (TLDCLK) is used to AC10 clock in the line DCC. Y11 TLDCLK is a 576 kHz clock used to sample the TLD AA11 input. TLDCLK is generated by gapping a 2.16 MHz clock. This pin is available independently for each channel. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 24 ...
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... TDAT[15:0] is considered valid only when TENB is D19 simultaneously asserted and the S/UNI-TETRA is C20 selected via TADR[4:0]. D21 TDAT[15:0] is sampled on the rising edge of E20 TFCLK. C23 D22 E21 D23 E22 F21 G20 E23 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 25 ...
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... Odd or even parity selection is made independently for each channel using the RXPTYP register bit. TPRTY is considered valid only when TENB is simultaneously asserted and the S/UNI-TETRA is selected via TADR[4:0]. TPRTY is sampled on the rising edge of TFCLK PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 26 ...
Page 47
... TSOP indicates the first word of a packet. TSOP is required to be present at the beginning of every packet for proper operation. TSOP is considered valid only when TENB is simultaneously asserted and the S/UNI-TETRA is selected via TADR[4:0]. TSOP is sampled on the rising edge of TFCLK. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 27 ...
Page 48
... PHY to transfer to. Byte level transfer works on a cycle basis. When TENB is asserted, data is transferred to the selected PHY. Nothing happens when TENB is deasserted. Polling is not available and packet availability is indicated by DTPA[4:1]. TENB is sampled on the rising edge of TFCLK. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 28 ...
Page 49
... TENB signal. G23 In packet level transfer mode, TADR[4:0] is also used for polling on PTPA. Note that address 0x1F is the null-PHY address and cannot be assigned to any port on the S/UNI-TETRA. TADR[4:0] is sampled on the rising edge of TFCLK. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 29 ...
Page 50
... TCA is tri-stated when either the null-PHY address (0x1F address not matching the address space set by PHY_ADR[2:0] is latched from the TADR[4:0] inputs when TENB is high. TCA is updated on the rising edge of TFCLK. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 30 ...
Page 51
... PHY_ADR[2:0] is latched from the TADR[4:0] inputs when TENB is high. PTPA is only available in POS-PHY packet-level transfer mode, as selected by the POS_PLVL register bit. PTPA is tristated in byte-level transfer mode. PTPA is updated on the rising edge of TFCLK. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 31 ...
Page 52
... TFCLK cycles MHz or lower instantaneous rate. K20 POS-PHY Transmit FIFO Write Clock (TFCLK). This signal is used to write packet octets into the 256 bytes packet FIFO’s. TFCLK cycles MHz or lower instantaneous rate. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 32 ...
Page 53
... Note that regardless of what fill level DTCA is set to indicate "full" at, the transmit cell processor can store 4 complete cells DTCA[4:1] are updated on the rising edge of TFCLK. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 33 ...
Page 54
... MSB’s, LSB’s are discarded) while TMOD set low indicates a 2-byte word. TMOD is considered valid only when TENB is simultaneously asserted and the S/UNI-TETRA is selected via TADR[4:0]. TMOD is sampled on the rising edge of TFCLK. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 34 ...
Page 55
... Packets marked with TERR will be appended with the abort sequence (0x7D-0x7E) when transmission. TERR is considered valid only when TENB is simultaneously asserted and the S/UNI-TETRA is selected via TADR[4:0]. TERR is sampled on the rising edge of TFCLK. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 35 ...
Page 56
... RDAT[15:0] is also tristated when either the null- V21 PHY address (0x1F address not matching W22 the address space is latched from the RADR[4:0] Y23 inputs. W21 Y22 RDAT[15:0] is updated on the rising edge of AA23 RFCLK. W20 Y21 AA20 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 36 ...
Page 57
... RSOC is tristated when RENB is deasserted. RSOC is also tristated when either the null-PHY address (0x1F address not matching the address space is latched from the RADR[4:0] inputs when RENB is high. RSOC is sampled on the rising edge of RFCLK. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 37 ...
Page 58
... RENB must operate in conjunction with RFCLK to access the FIFO’ high enough rate to prevent FIFO overflows. The system may de-assert RENB at anytime it is unable to accept another byte. RENB is sampled on the rising edge of RFCLK. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 38 ...
Page 59
... FIFO whose cell available signal is visible T22 on the RCA output. Note that address 0x1F is the null-PHY address and will not be identified to any port on the S/UNI-TETRA. RADR[4:0] is sampled on the rising edge of RFCLK. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 39 ...
Page 60
... PHY in use. RCA is tristated when either the null-PHY address (0x1F address not matching the address space is latched from the RADR[4:0] inputs when RENB is high. RCA is updated on the rising edge of RFCLK. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 40 ...
Page 61
... PRPA is only available in POS-PHY packet-level transfer mode, as selected by the POS_PLVL register bit. PRPA is tristated in byte-level transfer mode. PRPA is updated on the rising edge of RFCLK. Note: In some conditions RPA can assert prematurely. Refer to section 10.15.2.1. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 41 ...
Page 62
... POS-PHY Receive FIFO Read Clock (RFCLK). This signal is used to read packets from the receive FIFO’s. RFCLK must cycle MHz or lower instantaneous rate, but at a high enough rate to avoid FIFO overflows. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 42 ...
Page 63
... DRPA is otherwise low. The polarity of DRPA can be inverted with the RPAINV register bit. DRPA[x] is updated on the rising edge of RFCLK. Note: In some conditions RPA can assert prematurely. Refer to section 10.15.2.1. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 43 ...
Page 64
... REOP is tristated when RENB is deasserted. REOP is also tristated when either the null-PHY address (0x1F address not matching the address space is latched from the RADR[4:0] inputs when RENB is high. REOP is updated on the rising edge of RFCLK. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 44 ...
Page 65
... PHY_OEN must be tied to logic zero, and the PHY_EN register bit used to enable the bus once its PHY_ADR[2:0] is programmed in order to avoid conflicts. The PHY Output Enable does not tristate the DTCA, DTPA, DRCA, DRPA pins. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 45 ...
Page 66
... Except for S/UNI-TETRA global registers, the A[9:8] A14 bits allow to select which channel is being D13 accessed. The A[7:0] bits allow to select which C13 register is being access within a given channel B13 address space. A13 C12 B12 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 46 ...
Page 67
... INTB is an open drain output. Pin Function No. B8 The test clock (TCK) signal provides timing for test operations that are carried out using the IEEE P1149.1 test access port. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 47 ...
Page 68
... RSTB input. Pin Function No. B4 The analog CP and CN pins are provided for C5 applications that must meet SONET/SDH jitter K2 transfer specifications. A 220 nF X7R 10% ceramic K1 capacitor can be attached across CP and CN AB4 AA5 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 48 ...
Page 69
... I/O pads so that the pads can tolerate 5V on their inputs without forward biasing internal ESD protection devices. When BIAS is tied to +3.3V, the inputs and bi-directional inputs will only tolerate 3.3V level inputs. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 49 ...
Page 70
... The digital power (VDD) pins should be connected A23 to a well-decoupled +3 supply. B2 B22 C3 C21 D12 D15 D18 D20 F4 F20 J4 J20 M4 M20 R4 R20 V4 V20 Y12 Y15 Y18 Y20 AA3 AA21 AB2 AB22 AC1 AC23 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 50 ...
Page 71
... The digital ground (VSS) pins should be connected A6 to ground. A8 A12 A16 A18 A22 B1 B3 B21 B23 C2 C22 F1 F23 H1 H23 M1 M23 T1 T23 V1 V23 AA2 AA22 AB1 AB3 AB21 AB23 AC2 AC6 AC8 AC12 AC16 AC18 AC22 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 51 ...
Page 72
... RAVD3_C - Channel #3 CRU Y3 RAVD4_A - Channel #4 PECL Input Buffer AC4 RAVD4_B - Channel #4 CRU AA4 RAVD4_C - Channel #4 CRU L3 TAVD1_A - CSU L1 TAVD1_B - CSU The analog power (AVD) pins for the analog core. AVD should be connected to analog +3.3V. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 52 ...
Page 73
... RAVS3_C - Channel #3 CRU W4 RAVS4_A - Channel #4 PECL Input Buffer AC3 RAVS4_B - Channel #4 CRU Y5 RAVS4_C - Channel #4 CRU L2 TAVS1_A - CSU M3 TAVS1_B - CSU The analog ground (AVS) pins for the analog core. AVS should be connected to analog GND. PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 53 ...
Page 74
... RSD, RSDCLK, TSD, TSDCLK. RLD, RLDCLK, TLD, TLDCLK., D[7:0], A[10:0], WRB, RDB, CSB, RSTB, INTB, ALE, TRSTB, TCK, TMS, TDI, TDO, PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 54 ...
Page 75
... The total loop dynamics of the clock recovery PLL yield a jitter tolerance that exceeds the minimum tolerance proposed for SONET equipment by GR-253-CORE (Figure 3). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 55 ...
Page 76
... In addition, it extracts the section data communication channel from the section overhead and, if selected, provides it serially on output RSD. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 10000 100000 Jitter Freq. (Hz) PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 1000000 10000000 56 ...
Page 77
... Differences indicate that a section level bit error has occurred 64000 (8 x 8000) bit errors can be detected per second. The Error Monitor Block PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 57 ...
Page 78
... Line RDI is removed when any pattern other than 110 is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. The LRDI signal is PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 58 ...
Page 79
... TIP register bit feature. During a transfer, the counter value is latched and the counter is reset to PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 59 ...
Page 80
... During a read, the counter value is latched and the counter is reset there is an outstanding PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 60 ...
Page 81
... Within the pointer interpretation algorithm three states are defined as shown below: NORM_state (NORM) AIS_state (AIS) LOP_state (LOP) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 61 ...
Page 82
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE eq_new_point NDF_enable NORM eq_new_point AIS_ind 3 x AIS_ind 8 x inv_point disabled NDF + ss + offset value equal to active offset PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA eq_new_point NDF_enable AIS 62 ...
Page 83
... NDF_enable, and not AIS_ind, and not inc_ind and not dec_ind) disabled_NDF + ss + offset value in range 782 but not equal to active offset majority of I bits inverted + no majority of D bits inverted majority of D bits inverted + no majority of I bits inverted PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 63 ...
Page 84
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Description offset adjustment (increment or decrement indication) three consecutive equal new_point indications single NDF_enable indication three consecutive AIS indications eight consecutive inv_point indications eight consecutive NDF_enable indications PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 64 ...
Page 85
... The Error Monitor Block contains two 16-bit counters that are used to accumulate path BIP-8 errors (B3), and far end block errors (FEBEs). The contents of the two PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 65 ...
Page 86
... The cell delineation algorithm searches the 53 possible cell boundary candidates individually to determine the valid cell boundary location. While PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 66 ...
Page 87
... These values result in an average time to delineation of 33.66 µs for the STS-3c (STM-1) rate. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 correct HCS (byte by byte) Incorrect HCS (cell by cell) SYNC PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) PRESYNC DELTA consecutive correct HCS's (cell by cell) 67 ...
Page 88
... Figure 6. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE added (modulo 2) to the received HCS PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA polynomial. The ...
Page 89
... Cell) CORRECTION Single-Bit Error MODE (Correct Error and Pass Cell) DETECTION MODE No Errors Detected In M Cells th (Pass M Cell) No Errors Detected (Pass Cell) PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) ALPHA consecutive incorrect HCS's (To HUNT state) Errors Detected (Drop Cell) 69 ...
Page 90
... This block removes the Flag Sequence and passes the data onto the Byte Destuffing block. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA De-scrambling is ...
Page 91
... CRC polynomial is used. The CRC algorithm for the frame PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 FCS Packet POS Fram e Table 3: Byte Destuffing Escaped 7D-5E 7D-5D 7D-7E PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) Flag Flag 71 ...
Page 92
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE Figure 8: CRC Decoder PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA n n ...
Page 93
... The Transmit Line Interface allows to directly interface the S/UNI-TETRA with optical modules (ODLs) or other medium interfaces. This block performs clock PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 73 ...
Page 94
... TSOP) accessed through the microprocessor interface. Activation or deactivation of line AIS insertion is synchronized to frame boundaries. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 74 ...
Page 95
... All zeros may be continuously inserted (after scrambling) under register control for diagnostic purposes. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA ...
Page 96
... The Line FEBE Insert Block accumulates line BIP-24 errors (B2) detected by the Receive Line Overhead Processor and encodes far end block error indications in the transmit M1 byte. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 76 ...
Page 97
... The pointer value is used to insert the path overhead into the transmit stream. The current pointer value may be read via internal registers. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 77 ...
Page 98
... The cell headers are transmitted unscrambled, and the scrambler may optionally be disabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA ...
Page 99
... Overruns can be avoided by setting the high and low watermarks. The optimal setup depends on the system design. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 79 ...
Page 100
... The first FCS bit transmitted is the coefficient of the highest term. When PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 FCS Packet POS Fram PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) Flag Flag ...
Page 101
... On reset, the scrambler is set to all ones to ensure scrambling on start-up. The PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Figure 10: CRC Generator Parity Check Digits Table 4: Byte Stuffing Escaped 7D-5E 7D-5D 7D-7E PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) g n-1 Message D n-1 MSB 81 ...
Page 102
... If the phase of the start of frame shifts, the framer adjusts accordingly and resets the persistency counter and increments the unstable counter. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 82 ...
Page 103
... A path signal label unstable alarm or a synchronization status unstable alarm is declared when either unstable counter reaches five. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 83 ...
Page 104
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Table 5: OBR Mismatch Mechanism Receive Action 00 00 Match 00 01 Mismatch 00 XX Mismatch 01 00 Mismatch 01 01 Match 01 XX Match XX 00 Mismatch XX 01 Match XX XX Match XX YY Mismatch PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 84 ...
Page 105
... Interface is an extension to the UTOPIA 2 interface defined for the transfer of POS frames. Both the POS-PHY Byte-Level and Packet-Level transfer modes are supported. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 85 ...
Page 106
... RPA will assert between RFCLK clock cycles before the data is available and will remain asserted for RFCLK clock cycles. This is shown in Figure 11. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 86 ...
Page 107
... FIFO depth may be programmed to four, three, two, or one cells. The FIFO PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 00 Assertion of RENB due to RPA assertion No data Pre-mature RPA Width FIFO Cycles PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) Assertion of RENB Real RPA assertion 87 ...
Page 108
... FIFO from the system interface; the TADR[4:0] bus is used in polling to select the desired PHY device; the TPRTY signal determines the parity on the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 88 ...
Page 109
... The phase comparison between the reference clock (RCLK ) and the variable clock (or VCXO clock, VCOCLK) is implemented by sampling at a fixed interval, the Reference Period of Phase Counter output. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 89 ...
Page 110
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 VCO CLK RPHALFLG REACQ UISIT ION RPHALFLG PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) PHASE CO UNTER R PHASE SAMPLE REG ISTER E N ...
Page 111
... Reference Period times the programmed number of phase samples. At the end of this period, the accumulated phase sample value is transferred to the Phase PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 SAMPLEN EO C TIMFLG PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) PHSAMP[15:0] SAMPLE ACCUMULATO ...
Page 112
... S/UNI-TETRA Master Reset and Identity S/UNI-TETRA Master Configuration S/UNI-TETRA Master System Interface Config S/UNI-TETRA Master Clock Monitor S/UNI-TETRA Master Interrupt Status 305 S/UNI-TETRA Channel Reset and Performance Monitoring Update 206 S/UNI-TETRA Channel Configuration PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) Description 92 ...
Page 113
... TLOP Transmit K1 323 TLOP Transmit K2 324 S/UNI-TETRA Channel Transmit Synchronization Message (S1) 325 S/UNI-TETRA Channel Transmit J0/Z0 326 Reserved 327 Reserved 328 SSTB Control 329 SSTB Status 32A SSTB Indirect Address PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) Description (Clock 93 ...
Page 114
... TPOP Arbitrary Pointer LSB 346 TPOP Arbitrary Pointer MSB 347 TPOP Path Trace 348 TPOP Path Signal Label 349 TPOP Path Status 34A TPOP Reserved 34B TPOP Reserved 34C TPOP Reserved 34D TPOP Reserved PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) Description 94 ...
Page 115
... RXCP Received Cell Count MSB 36E RXCP Idle Cell Count LSB 36F RXCP Idle Cell Count 370 RXCP Idle Cell Count MSB 371 RXCP Reserved 372 RXCP Reserved 373 RXCP Reserved PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) Description 95 ...
Page 116
... S/UNI-TETRA Channel Receive RDI and Enhanced RDI Control Extensions 394 S/UNI-TETRA Channel Receive Line AIS Control 395 S/UNI-TETRA Channel Receive Path AIS Control 396 S/UNI-TETRA Channel Receive Alarm Control #1 397 S/UNI-TETRA Channel Receive Alarm Control #2 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) Description 96 ...
Page 117
... RXFP-50 Max Length Frame Count (LSB) 3B6 RXFP-50 Max Length Frame Count (MSB) 3B7 RXFP-50 Reserved 3B8 RXFP-50 Reserved 3B9 RXFP-50 Reserved 3BA RXFP-50 Reserved 3BB RXFP-50 Reserved 3BC RXFP-50 Reserved 3BD RXFP-50 Reserved PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) Description 97 ...
Page 118
... WANS Reserved 3D8 WANS Reserved 3D9 WANS Reference Period (LSB) 3DA WANS Reference Period (MSB) 3DB WANS Phase Counter Period (LSB) 3DC WANS Phase Counter Period (MSB) 3DD WANS Phase Average Period PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) Description 98 ...
Page 119
... RASE APS K2 3F7 RASE Synchronization Status S1 3F8 Reserved 3F9 Reserved 3FA Reserved 3FB Reserved 3FC Reserved 3FD Reserved 3FE Reserved 3FF Reserved S/UNI-TETRA Master Test Register 701 Reserved for Test - 7FF PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) Description 99 ...
Page 120
... Addresses that are not shown must be treated as Reserved. • A[10] is the test resister select (TRS) and should be set to logic zero for normal mode register access. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 100 ...
Page 121
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Exceptions to this rule are indicated by the PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 101 ...
Page 122
... Otherwise, the effect of a software reset is equivalent to that of a hardware reset. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default ID[2] 0 ID[1] 1 ID[0] 0 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 102 ...
Page 123
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default Table 8: TFPO Channel Selection Selected Channel 00 Channel #1 01 Channel #2 10 Channel #3 11 Channel #4 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 103 ...
Page 124
... PECL receivers are configured to operate with a 5.0V input voltage. Reserved: The reserved bits must be programmed to their default value proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 104 ...
Page 125
... The PHY_ADR[2:0] is Device Identification Address (PHY_ADR[2:0]). The PHY_ADR[2:0] register bits are the most-significant bits of the address space PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 105 ...
Page 126
... Note that the null-PHY address 0x1F is the null-PHY address and cannot be assigned to any port on the S/UNI-TETRA. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 106 ...
Page 127
... TCLKA is set high on a rising edge of TCLK, and is set low when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 107 ...
Page 128
... RCLK4 output. RCLK4A is set high on a rising edge of RCLK4, and is set low when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 108 ...
Page 129
... The CHNL4I bit is high when an interrupt request is active from the channel #4. The Channel #4 Interrupt Status register should be read to identify the source of the interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 109 ...
Page 130
... Synthesis and PISO block (CSPI, Clock Synthesis Unit). The CSUI interrupt sources are enabled in the Clock Synthesis Interrupt Control/Status Register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 110 ...
Page 131
... Setting the Channel Reset for channels 2 through 4 has no effect on global registers. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default TIP X PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 111 ...
Page 132
... Each alarm can individually be enabled and disabled using the S/UNI-TETRA Channel Auto Path RDI Control Registers. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 112 ...
Page 133
... FEBE is inserted for each line BIP error event, respectively. When AUTOLFEBE is set to logic zero, incoming line BIP error events do not generate FEBE events. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 113 ...
Page 134
... TSOP Control register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default LLE PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 114 ...
Page 135
... TFPI_EN should always be set to logic zero when the channel is loop-timed (LOOPT set to logic one line loopback (LLE set to logic one). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 115 ...
Page 136
... This register controls the timing and high speed loopback features of the S/UNI-TETRA. Reserved: The reserved bits must be programmed to their default value proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 116 ...
Page 137
... The RXCPI bit is high when an interrupt request is active from the RXCP block. The RXCP interrupt sources are enabled in the RXCP Interrupt Enable/Status Register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 117 ...
Page 138
... The RASEI bit is high when an interrupt request is active from the RASE block. The RASE interrupt sources are enabled in the RASE Interrupt Enable Register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 118 ...
Page 139
... The RXFPI bit is high when an interrupt request is active from the RXFP block. The RXFP interrupt sources are enabled in the RXFP Interrupt Enable/Status Register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 119 ...
Page 140
... The TXFPI bit is high when an interrupt request is active from the TXFP block. The TXFP interrupt sources are enabled in the TXFP Interrupt Control/Status Register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 120 ...
Page 141
... Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 121 ...
Page 142
... Bit 0 R/W Reserved Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 122 ...
Page 143
... When RROOLV is a logic zero, the CRU is locked to the receive reference. The RROOLV bit may remain set at logic one for several PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 123 ...
Page 144
... Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 124 ...
Page 145
... The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PLL Mode Select Reserved Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) areis an external pins. 125 ...
Page 146
... STS mode; all other framing bits are ignored. When a logic zero is written to the ALGO2 bit position, the framer is PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 126 ...
Page 147
... B1 byte are accumulated in the B1 error counter. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 127 ...
Page 148
... This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 128 ...
Page 149
... The BIPEI bit is the section BIP-8 interrupt status bit. BIPEI is set high when a section layer (B1) bit error is detected. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 129 ...
Page 150
... RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 130 ...
Page 151
... When logic zero, scrambling is enabled. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 131 ...
Page 152
... The DLOS bit controls the insertion of all zeros in the transmit stream. When DLOS is set to logic one, the transmit stream is forced to 0x00. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default DFP 0 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 132 ...
Page 153
... B2 bit error that occurs during that frame. The accumulation of B2 error events functions independently and is controlled by the BIPWORD register bit.. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 133 ...
Page 154
... B2 bit error that occurs during that frame (the counter can be incremented times per frame). Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 134 ...
Page 155
... The LAISE bit is an interrupt enable for line AIS. When LAISE is set to logic one, an interrupt is generated when line AIS changes state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 135 ...
Page 156
... The FEBEE bit is an interrupt enable for the line far end block errors. When FEBEE is set to logic one, an interrupt is generated when FEBE (M1) is detected. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 136 ...
Page 157
... Bit 2 R LBE[10] Bit 1 R LBE[9] Bit 0 R LBE[8] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 137 ...
Page 158
... RSOP, RLOP, RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 138 ...
Page 159
... Bit 2 R LFE[10] Bit 1 R LFE[9] Bit 0 R LFE[8] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 139 ...
Page 160
... RSOP, RLOP, RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 140 ...
Page 161
... TLOP Transmit K1 Register and the TLOP Transmit K2 Register. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 141 ...
Page 162
... The DBIP bit controls the insertion of bit errors continuously in the line BIP byte(s) (B2). When DBIP is set to logic one, the B2 byte(s) are inverted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 142 ...
Page 163
... Successive writes to this register must be spaced at least two frames (250 µs) apart. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 143 ...
Page 164
... APS code value is ensured by writing the desired K2 APS code value to this register before writing the TLOP Transmit K1 Register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 144 ...
Page 165
... Reserved The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 145 ...
Page 166
... Z0[7] is the most significant bit corresponding to bit 1, the first bit transmitted. Z0[0] is the least significant bit, corresponding to bit 8, the last bit transmitted.. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 146 ...
Page 167
... TNULL should be set high before changing the contents of the trace buffer to avoid sending partial messages. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 147 ...
Page 168
... TIM states. When ZEROEN is set low, all ZERO’s section trace message strings are ignored. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 148 ...
Page 169
... BUSY is set to a logic one immediately upon writing to the SSTB Indirect Address register, and stays high until the initiated PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 149 ...
Page 170
... This register should be polled to determine when new data is available in the SSTB Indirect Data register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 150 ...
Page 171
... Data register. When RWB is a logic zero, a write access is initiated. The data in the SSTB Indirect Data register is written to the addressed location in the selected buffer. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default 0 A[6] 0 A[5] 0 A[4] 0 A[3] 0 A[2] 0 A[1] 0 A[0] 0 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 151 ...
Page 172
... The data that is written to a buffer is set up in this register before initiating the indirect write operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default D[7] 0 D[6] 0 D[5] 0 D[4] 0 D[3] 0 D[2] 0 D[1] 0 D[0] 0 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 152 ...
Page 173
... S/UNI-TETRA DATASHEET PMC-1971240 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 153 ...
Page 174
... S/UNI-TETRA DATASHEET PMC-1971240 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 154 ...
Page 175
... The PAISV bit is read to determine the path AIS state. When PAISV is a logic one, the S/UNI-TETRA has declared path AIS. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 155 ...
Page 176
... When LOPCONV is a logic one, the S/UNI-TETRA has declared loss of pointer concatenation. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 156 ...
Page 177
... When the PSL5 is set low, the PSL is updated when the same value is received for 3 consecutive frames. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 157 ...
Page 178
... AIS state occurs. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 158 ...
Page 179
... RPOP Path Signal Label register. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 159 ...
Page 180
... The ERDII bit is set to logic one when a change is detected in the received enhanced RDI state. ERDII is cleared when the RPOP Interrupt Status register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 160 ...
Page 181
... INVNDFI is a logic one when an illegal NDF field value is detected in the receive payload pointer. An illegal NDF field is any one of the following six PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 161 ...
Page 182
... ILLJREQI is a logic one when the pointer interpreter detects an illegal pointer justification request event. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 162 ...
Page 183
... The PAISE bit is the interrupt enable for path AIS. When PAISE is a logic one, an interrupt is generated when the path AIS state changes. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 163 ...
Page 184
... When PSLE is a logic one, an interrupt is generated when the received C2 byte changes. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 164 ...
Page 185
... ERDIE: When EREDIE is a logic one, an interrupt is generated when a path Enhanced RDI is detected. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 165 ...
Page 186
... When a logic one is written to the DISCOPAE interrupt enable bit position, a change of pointer alignment event will activate the interrupt output, INTB. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 166 ...
Page 187
... INTB. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 167 ...
Page 188
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 168 ...
Page 189
... LOP when the pointer is out of range, no active offset change will occur. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 169 ...
Page 190
... The EXTD bit extends the registers to facilitate additional mapping. If this bit is set to logic one the register mapping, for registers 0x30, 0x31 and 0x33, are extended. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 170 ...
Page 191
... PSL5 bit. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 171 ...
Page 192
... The count can also be polled by writing to the S/UNI-TETRA Channel Reset and Monitoring Update register (0x05). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 172 ...
Page 193
... The count can also be polled by writing to the S/UNI-TETRA Channel Reset and Monitoring Update register (0x05). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 173 ...
Page 194
... Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 174 ...
Page 195
... When SOS is a logic zero, PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 175 ...
Page 196
... Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 176 ...
Page 197
... S/UNI-TETRA DATASHEET PMC-1971240 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 177 ...
Page 198
... EPRDIEN is logic zero, the extended RDI bits of the G1 byte not overwritten by the TPOP block, regardless of EPRDISRC. When EPRDIEN is logic one PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 178 ...
Page 199
... G1[7:5] bits are used to indicate PRDI. The actual three bit code will be controlled according to the EPRDISRC. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 179 ...
Page 200
... The new data flag bit positions are set to the programmed NDF PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Default PLD 0 NDF 0 NSE 0 PSE 0 0 PM5351 S/UNI TETRA SATURN USER NETWORK INTERFACE (155 TETRA) 180 ...