MC68HC708MP16CFU Freescale Semiconductor, Inc, MC68HC708MP16CFU Datasheet
MC68HC708MP16CFU
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MC68HC708MP16 Data Sheet M68HC08 Microcontrollers Rev. 3.1 MC68HC708MP16/D July 28, 2005 freescale.com ...
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Technical Data — MC68HC708MP16 Section 1. General Description . . . . . . . . . . . . . . . . . . . 29 Section 2. Memory Map . . . . . . . . ...
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List of Sections Section 18. Low-Voltage Inhibit (LVI 347 Section 19. Analog-to-Digital Converter (ADC 353 Section 20. Power-On Reset (POR ...
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Technical Data — MC68HC708MP16 1.1 1.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.5.10 1.5.11 1.5.12 1.5.13 1.5.14 1.5.15 1.5.16 1.5.17 MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor Section 1. General Description Contents . . . ...
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Table of Contents 2.1 2.2 2.3 2.4 3.1 3.2 3.3 4.1 4.2 4.3 4.4 4.5 5.1 5.2 5.3 6.1 6.2 6.3 Technical Data 6 Section 2. Memory Map Contents . . . . . . . . . . . ...
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MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor CPU Registers ...
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Table of Contents 7.7 7.7.1 7.7.2 7.7.3 7.7.4 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.2.1 8.4.2.2 8.4.2.3 8.4.2.4 8.4.2.5 8.4.3 8.4.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.5.7 8.5.8 8.6 8.6.1 8.6.2 8.6.3 8.7 8.8 Technical Data 8 Low-Power ...
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MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor CGM During Break Mode ...
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Table of Contents 9.8 9.9 9.10 9.11 9.11.1 9.11.2 9.11.3 9.11.4 9.11.5 9.11.6 9.11.7 9.11.8 9.11.9 9.11.10 9.11.11 9.12 10.1 10.2 10.3 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 Technical Data 10 Initialization and the PWMEN Bit . . . ...
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MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor Section 11. Timer Interface Module A ...
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Table of Contents 12.4 12.4.1 12.4.2 12.4.3 12.4.3.1 12.4.3.2 12.4.4 12.4.4.1 12.4.4.2 12.4.4.3 12.5 12.6 12.7 12.8 12.8.1 12.8.2 12.9 12.9.1 12.9.2 12.9.3 12.9.4 12.9.5 Section 13. Serial Peripheral Interface Module (SPI) 13.1 13.2 13.3 13.4 13.5 13.5.1 13.5.2 Technical ...
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Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 14.4 14.4.1 14.4.2 14.4.2.1 14.4.2.2 14.4.2.3 14.4.2.4 14.4.2.5 14.4.2.6 14.4.3 14.4.3.1 14.4.3.2 14.4.3.3 14.4.3.4 14.4.3.5 14.4.3.6 14.4.3.7 14.5 14.6 14.7 14.7.1 14.7.2 14.8 14.8.1 14.8.2 14.8.3 14.8.4 14.8.5 14.8.6 14.8.7 15.1 15.2 Technical Data 14 Functional Description ...
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MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor Port A . ...
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Table of Contents 17.1 17.2 17.3 17.4 17.5 17.6 17.7 18.1 18.2 18.3 18.4 18.4.1 18.4.2 18.4.3 18.5 18.6 18.7 19.1 19.2 19.3 19.4 19.4.1 19.4.2 19.4.3 Technical Data 16 Section 17. External Interrupt (IRQ) Contents . . . . ...
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MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor Continous Conversion . . . . . ...
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Table of Contents 21.10 Clock Generation Module Electrical Characteristics 375 21.11 Analog-to-Digital Converter (ADC) Characteristics 377 21.12 Memory Characteristics . . . . . . ...
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Technical Data — MC68HC708MP16 Figure 1-1 1-2 1-3 1-4 2-1 2-2 4-1 5-1 6-1 6-2 6-3 6-4 6-5 6-6 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor Title MCU Block Diagram. ...
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List of Figures Figure 7-12 7-13 7-14 7-15 7-16 7-17 8-1 8-2 8-3 8-4 8-5 8-6 8-7 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 Technical Data ...
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Figure 9-22 9-23 9-24 9-25 9-26 9-27 9-28 9-29 9-30 9-31 9-32 9-33 9-34 9-35 9-36 9-37 9-38 9-39 9-40 9-41 9-42 9-43 9-44 9-45 9-46 9-47 9-48 9-49 9-50 9-51 9-52 10-1 10-2 MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor ...
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List of Figures Figure 10-3 10-4 10-5 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 Technical Data 22 Title Sample Monitor Waveforms ...
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Figure 13-9 13-10 13-11 13-12 13-13 13-14 13-15 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 15-13 MC68HC708MP16 Rev. 3.1 — Freescale ...
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List of Figures Figure 15-14 15-15 15-16 15-17 15-18 16-1 16-2 16-3 17-1 17-2 17-3 17-4 18-1 18-2 18-3 19-1 19-2 19-3 19-4 20-1 21-1 21-2 22-1 Technical Data 24 Title Data Direction Register E (DDRE ...
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Technical Data — MC68HC708MP16 Table 2-1 6-1 6-2 7-1 7-2 8-1 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 10-1 10-2 10-3 10-4 10-5 10-6 10-7 MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor Title Vector Addresses ................................................................ 51 ...
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List of Tables Table 10-8 10-9 11-1 11-2 12-1 12-2 13-1 13-2 13-3 13-4 14-1 14-2 14-3 14-4 14-5 14-6 14-7 15-1 15-2 15-3 15-4 15-5 15-6 18-1 19-1 19-2 21-1 21-2 Technical Data 26 Title RUN (Run User Program) ...
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Table 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 21-11 21-12 23-1 MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor Title Thermal Characteristics .....................................................369 DC Electrical Characteristics = 5.0 Vdc ± 10%) .................................................. 370 ( 5.0 Vdc ± 10%)............................... 371 ...
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List of Tables Technical Data 28 MC68HC708MP16 List of Tables Rev. 3.1 — Freescale Semiconductor ...
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Technical Data — MC68HC708MP16 1.1 Contents 1.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.5.10 1.5.11 1.5.12 1.5.13 1.5.14 1.5.15 1.5.16 1.5.17 MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor Section 1. General Description Introduction . . ...
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General Description 1.2 Introduction The MC68HC708MP16 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the ...
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Features of the CPU08 include: • • • • • • • • • • 1.4 MCU Block Diagram Figure 1-1 MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor Clock Generator module (CGM) Digitally filtered low-voltage ...
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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 96 BYTES USER EPROM — 16,384 BYTES USER RAM — 512 BYTES MONITOR ROM ...
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Pin Assignments Figure 1-2 PTB2/ATD2 1 PTB3/ATD3 2 PTB4/ATD4 3 PTB5/ATD5 4 PTB6/ATD6 5 PTB7/ATD7 6 PTC0/ATD8 7 PTC1/ATD9 DDAD DDAREF V 10 SSAD V 11 REFL V 12 ADCAP PTC2 13 PTC3 14 PTC4 ...
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General Description 1.5.1 Power Supply Pins ( and V DD from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to ...
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Integration Module 1.5.4 External Interrupt Pin (IRQ1/V IRQ1/V External Interrupt programming power pin. (See 1.5.5 CGM Power Supply Pins (V V DDA clock generator module (CGM). Decoupling of these pins should be as ...
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General Description 1.5.9 ADC Voltage Reference Low Pin (V V REFL to the same voltage potential as V Digital Converter 1.5.10 Port A Input/Output (I/O) Pins (PTA7–PTA0) PTA7–PTA0 are general-purpose bidirectional I/O port pins. (See Section 15. Input/Output (I/O) 1.5.11 ...
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PWM Pins (PWM6–PWM1) PWM6–PWM1 are dedicated pins used for the outputs of the pulse width modulator module (PWMMC). These are high current pins capable sink (V Section 9. Pulse Width Modulator for Motor Control (PWMMC) Section ...
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General Description Technical Data 38 General Description MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor ...
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Technical Data — MC68HC708MP16 2.1 Contents 2.2 2.3 2.4 2.2 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in • • • • MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor Section 2. Memory Map Introduction ...
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Memory Map Technical Data 40 $0000 ↓ I/O REGISTERS (96 BYTES) $004F $0050 ↓ RAM (512 BYTES) $024F $0250 ↓ UNIMPLEMENTED (48,048 BYTES) $BDFF $BE00 ↓ EPROM (16,384 BYTES) $FDFF $FE00 SIM BREAK STATUS REGISTER (SBSR) $FE01 SIM RESET STATUS ...
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Input/Output (I/O) Section Addresses $0000–$004F, shown in control, status, and data registers. Additional I/O registers have these addresses: • • • • • • • • • MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor $FE00 — SIM break status register, ...
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Memory Map Addr. Name Read: Port A Data Register $0000 (PTA) Write: See page 320. Reset: Read: Port B Data Register $0001 (PTB) Write: See page 322. Reset: Read: Port C Data Register $0002 (PTC) Write: See page 324. Reset: ...
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Addr. Name Data Direction Register E $000A (DDRE) See page 329. Data Direction Register F $000B (DDRF) See page 331. Timer A Status and Control Register (TASC) $000C See page 215. Timer A Counter Register High $000D (TACNTH) See page ...
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Memory Map Addr. Name Read: CH1F Timer A Channel 1 Status and $0014 Control Register (TASC1) Write: See page 223. Reset: Read: Timer A Channel 1 Register $0015 High (TACH1H) Write: See page 223. Reset: Read: Timer A Channel 1 ...
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Addr. Name IRQ Status and Control $001E Register (ISCR) See page 345. Configuration Write-Once Register (CONFIG) $001F See page 60. PWM Control Register 1 $0020 (PCTL1) See page 175. PWM Control Register 2 $0021 (PCTL2) See page 177. Fault Control ...
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Memory Map Addr. Name Read: PWM Counter Modulo Register $0028 High (PMODH) Write: See page 173. Reset: Read: PWM Counter Modulo Register $0029 Low (PMODL) Write: See page 173. Reset: Read: PWM 1 Value Register High $002A (PVAL1H) Write: See ...
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Addr. Name PWM 5 Value Register High $0032 (PVAL5H) See page 174. PWM 5 Value Register Low $0033 (PVAL5L) See page 174. PWM 6 Value Register High $0034 (PVAL6H) See page 174. PWM 6 Value Register Low $0035 (PVAL6L) See ...
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Memory Map Addr. Name Read: SCI Status Register 2 $003C (SCS2) Write: See page 313. Reset: Read: SCI Data Register $003D (SCDR) Write: See page 314. Reset: Read: SCI Baud Rate Register $003E (SCBR) Write: See page 314. Reset: Read: ...
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Addr. Name Timer B Channel 0 Register $0046 Low (TBCH0L) See page 248. Timer B Channel 1 Status and $0047 Control Register (TBSC1) See page 244. Timer B Channel 1 Register $0048 High (TBCH1H) See page 248. Timer B Channel ...
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Memory Map Addr. Name SIM Break Status Register Read: $FE00 (SBSR) Write: See page 99. Note: Writing a logic 0 clears SBSW. Reset: Read: SIM Reset Status Register $FE01 (SRSR) Write: See page 101. Reset: Read: SIM Break Flag Control ...
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Table 2-1 MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor is a list of vector locations. Table 2-1. Vector Addresses Address $FFD2 SCI Transmit Vector (High) $FFD3 SCI Transmit Vector (Low) $FFD4 SCI Receive Vector (High) $FFD5 SCI Receive Vector (Low) $FFD6 ...
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Memory Map 2.4 Monitor ROM The 240 bytes at addresses $FE10–$FEFF are reserved ROM addresses that contain the instructions for the monitor functions. (See Section 10. Monitor ROM Technical Data 52 Table 2-1. Vector Addresses (Continued) Address $FFF0 FAULT 4 ...
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Technical Data — MC68HC708MP16 Section 3. Random-Access Memory (RAM) 3.1 Contents 3.2 3.3 3.2 Introduction This section describes the 512 bytes of RAM. 3.3 Functional Description Addresses $0050–$024F are RAM locations. The location of the stack RAM is programmable. The ...
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Random-Access Memory (RAM) During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may ...
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Technical Data — MC68HC708MP16 4.1 Contents 4.2 4.3 4.4 4.5 4.2 Introduction This section describes the non-volatile memory (EPROM/OTPROM). 4.3 Functional Description An MCU with a quartz window has 16 Kbytes of erasable, programmable ROM (EPROM). The quartz window allows ...
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EPROM/OTPROM 4.4 EPROM/OTPROM Control Register The EPROM control register controls EPROM/OTPROM programming. Address: $FE07 Read: Write: Reset: Figure 4-1. EPROM/OTPROM Control Register (EPMCR) ELAT — EPROM/OTPROM Latch Control Bit This read/write bit latches the address and data buses for programming ...
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EPROM/OTPROM Programming Sequence The unprogrammed state Programming changes the state Use the following procedure to program a byte of EPROM/OTPROM: 1. Apply V 2. Set the ELAT bit. NOTE: Writing logic 1s to ...
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EPROM/OTPROM Technical Data 58 EPROM/OTPROM MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor ...
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Technical Data — MC68HC708MP16 Section 5. Configuration Register (CONFIG) 5.1 Contents 5.2 5.3 5.2 Introduction This section describes the configuration register (CONFIG). This register contains bits that configure the following options: • • • • • • • MC68HC708MP16 Rev. ...
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Configuration Register (CONFIG) 5.3 Functional Description The configuration register is a write-once register. Out of reset, the configuration register will read all 0s. Once the register is written, further writes will have no effect until a reset occurs. NOTE: If ...
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INDEP — Independent Mode Enable Bit INDEP determines if the motor control PWMs will be six independent PWMs or three complementary PWM pairs. (See Width Modulator for Motor Control LVIPWR — LVI Power Disable Bit LVIPWR disables the LVI module. ...
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Configuration Register (CONFIG) Technical Data 62 Configuration Register (CONFIG) MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor ...
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Technical Data — MC68HC708MP16 6.1 Contents 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.5 6.6 6.7 6.2 Introduction This section describes the central processor unit (CPU08, Version A). The M68HC08 CPU is an enhanced and fully object-code-compatible version of ...
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Central Processor Unit (CPU) 6.3 Features Features of the CPU include the following: • • • • • • • • • • • 6.4 CPU Registers Figure 6-1 the memory map. Technical Data 64 Full upward, object-code compatibility with ...
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Accumulator (A) The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor ...
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Central Processor Unit (CPU) 6.4.2 Index Register (H:X) The 16-bit index register allows indexed addressing of a 64-Kbyte memory space the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit ...
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Stack Pointer (SP) The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the ...
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Central Processor Unit (CPU) 6.4.4 Program Counter (PC) The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location ...
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Condition Code Register (CCR) The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic one. The following paragraphs describe ...
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Central Processor Unit (CPU) I — Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set ...
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C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and ...
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Central Processor Unit (CPU) 6.6 Instruction Set Summary Table 6-1 Table 6-1. Instruction Set Summary Source Operation Form ADC #opr ADC opr ADC opr ADC opr,X Add with Carry ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD ...
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Table 6-1. Instruction Set Summary (Continued) Source Operation Form BCLR n, opr Clear Bit BCS rel Branch if Carry Bit Set (Same as BLO) BEQ rel Branch if Equal Branch if Greater Than or Equal To BGE ...
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Central Processor Unit (CPU) Table 6-1. Instruction Set Summary (Continued) Source Operation Form BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always BRCLR n,opr,rel Branch if Bit Clear BRN rel Branch ...
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Table 6-1. Instruction Set Summary (Continued) Source Operation Form CMP #opr CMP opr CMP opr CMP opr,X Compare A with M CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX Complement (One’s Complement) COM opr,X COM ,X ...
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Central Processor Unit (CPU) Table 6-1. Instruction Set Summary (Continued) Source Operation Form INC opr INCA INCX Increment INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X Jump JMP opr,X JMP ,X JSR opr JSR opr JSR ...
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Table 6-1. Instruction Set Summary (Continued) Source Operation Form NEG opr NEGA NEGX Negate (Two’s Complement) NEG opr,X NEG ,X NEG opr,SP NOP No Operation NSA Nibble Swap A ORA #opr ORA opr ORA opr ORA opr,X Inclusive OR A ...
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Central Processor Unit (CPU) Table 6-1. Instruction Set Summary (Continued) Source Operation Form SBC #opr SBC opr SBC opr SBC opr,X Subtract with Carry SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC Set Carry Bit SEI Set Interrupt Mask ...
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Table 6-1. Instruction Set Summary (Continued) Source Operation Form TST opr TSTA TSTX Test for Negative or Zero TST opr,X TST ,X TST opr,SP TSX Transfer SP to H:X TXA Transfer TXS Transfer H ...
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Bit Manipulation Branch DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA ...
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Technical Data — MC68HC708MP16 Section 7. System Integration Module (SIM) 7.1 Contents 7.2 7.3 7.3.1 7.3.2 7.3.3 7.4 7.4.1 7.4.2 7.4.2.1 7.4.2.2 7.4.2.3 7.4.2.4 7.4.2.5 7.5 7.5.1 7.5.2 7.6 7.6.1 7.6.1.1 7.6.1.2 7.6.2 7.6.3 7.7 7.7.1 7.7.2 7.7.3 7.7.4 MC68HC708MP16 ...
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System Integration Module (SIM) 7.2 Introduction This section describes the system integration module. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in The SIM is a system state controller that ...
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RESET PIN LOGIC RESET PIN CONTROL SIM RESET STATUS REGISTER MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor WAIT CONTROL SIM COUNTER ÷ 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER RESET CONTROL RESET INTERRUPT CONTROL AND PRIORITY DECODE Figure 7-1. SIM ...
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System Integration Module (SIM) Addr. Name Read: SIM Break Status Register $FE00 (SBSR) Write: Note: Writing a logic 0 clears SBSW. Reset: Read: SIM Reset Status Register $FE01 Write: (SRSR) Reset: Read: SIM Break Flag Control $FE03 Write: Register (SBFCR) ...
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SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in from either an external ...
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System Integration Module (SIM) 7.3.3 Clocks in Wait Mode In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if ...
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External Pin Reset Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming ...
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System Integration Module (SIM) 7.4.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for ...
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Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 ...
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System Integration Module (SIM) 7.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM ...
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Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the V level for at least nine consecutive CPU cycles. The LVI bit in the SIM reset status register (SRSR) is set, and ...
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System Integration Module (SIM) 7.6 Exception Control Normal, sequential program execution can be changed in three different ways: • • • 7.6.1 Interrupts At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and ...
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YES As many interrupts as exist on chip MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor FROM RESET YES BREAK INTERRUPT? I BIT SET BIT SET? NO INT0 YES INTERRUPT? NO INT11 YES INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR. ...
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System Integration Module (SIM) MODULE INTERRUPT I BIT IAB SP – 4 IDB CCR R/W 7.6.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When ...
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The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE: To maintain compatibility with the M6805 Family, the H register is not ...
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System Integration Module (SIM) 7.6.2 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 7.6.3 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during ...
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Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking ...
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System Integration Module (SIM) Figure 7-13 EXITSTOPWAIT NOTE: EXITSTOPWAIT = CGMXCLK Technical Data 98 and Figure 7-14 show the timing for WAIT recovery. IAB $6E0B $6E0C IDB $A6 $A6 $A6 $01 RST pin OR CPU interrupt OR break interrupt Figure ...
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SIM Break Status Register The SIM break status register contains a flag to indicate that a break caused an exit from wait mode. Address: Read: Write: Reset: NOTE 1. Writing a logic 0 clears SBSW. SBSW — SIM Break ...
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System Integration Module (SIM) ; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the break ; service routine software. ...
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SIM Reset Status Register This register contains six flags that show the source of the last reset. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in ...
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System Integration Module (SIM) 7.7.4 SIM Break Flag Control Register The SIM break control register contains a bit that enables software to clear status bits while the MCU break state. Address: Read: Write: Reset: BCFE — Break ...
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Technical Data — MC68HC708MP16 Section 8. Clock Generator Module (CGM) 8.1 Contents 8.2 8.3 8.4 8.4.1 8.4.2 8.4.2.1 8.4.2.2 8.4.2.3 8.4.2.4 8.4.2.5 8.4.3 8.4.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.5.7 8.5.8 8.6 8.6.1 8.6.2 8.6.3 8.7 8.8 8.9 ...
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Clock Generator Module (CGM) 8.10 8.10.1 8.10.2 8.10.3 8.10.4 8.2 Introduction This section describes the clock generator module (CGM, Version A). The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also ...
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Functional Description The CGM consists of three major submodules: • • • Figure 8-1 8.4.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the ...
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Clock Generator Module (CGM) CRYSTAL OSCILLATOR OSC2 OSC1 SIMOSCEN CGMRDV CGMRCLK V DDA PHASE DETECTOR LOCK DETECTOR LOCK CGMVDV Technical Data 106 CLOCK ÷ SELECT ³ CIRCUIT BCS CGMXFC V SS VRS[7:4] VOLTAGE LOOP CONTROLLED FILTER OSCILLATOR PLL ANALOG BANDWIDTH ...
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Addr. Name PLL Control Register $FE0B (PCTL) PLL Bandwidth Control $FE0C Register (PBWC) PLL Programming Register $FE0D (PPG) 8.4.2 Phase-Locked Loop Circuit (PLL) The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending ...
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Clock Generator Module (CGM) The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range from roughly ...
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Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: • • 8.4.2.3 Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop ...
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Clock Generator Module (CGM) The following conditions apply when the PLL is in automatic bandwidth control mode: • • • • • The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that ...
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Programming the PLL The following procedure shows how to program the PLL. NOTE: The round function in the following equations means that the real number should be rounded to the nearest integer number. 1. Choose the desired bus frequency, ...
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Clock Generator Module (CGM) NOTE: Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU. 9. Program the PLL registers accordingly: 8.4.2.5 Special Programming Exceptions The programming method described in does not account for possible exceptions. A ...
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VCO clock. The VCO clock also cannot be selected as the base clock source if the factor L is programmed to a zero. This value would set up a condition inconsistent with the operation of ...
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Clock Generator Module (CGM) SIMOSCEN OSC1 can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data. S Figure 8-3. CGM External Connections 8.5 I/O Signals The following paragraphs describe the ...
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NOTE: To prevent noise problems, C CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the C 8.5.4 PLL Analog Power Pin (V V DDA V DDA NOTE: Route V capacitors as close as ...
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Clock Generator Module (CGM) 8.5.8 CGM CPU Interrupt (CGMINT) CGMINT is the interrupt signal generated by the PLL lock detector. 8.6 CGM Registers The following registers control and monitor operation of the CGM: • • • Figure 8-4 PCTL $FE0B ...
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PLL Control Register The PLL control register contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit. Address: Read: Write: Reset: PLLIE — PLL Interrupt Enable Bit This read/write bit enables the PLL to ...
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Clock Generator Module (CGM) PLLON — PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See Circuit.) ...
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PLL Bandwidth Control Register The PLL bandwidth control register does the following: • • • • Address: Read: Write: Reset: AUTO — Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL ...
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Clock Generator Module (CGM) ACQ — Acquisition Mode Bit When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is ...
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PLL Programming Register The PLL programming register contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the VCO. Address: Read: Write: Reset: MUL[7:4] — Multiplier Select Bits These read/write bits ...
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Clock Generator Module (CGM) NOTE: The multiplier select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1). VRS[7:4] — VCO Range Select Bits These read/write bits control the hardware center-of-range linear ...
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Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables ...
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Clock Generator Module (CGM) 8.9 CGM During Break Mode The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables ...
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MHz ±5 kHz. Five kHz = 5% of the 100-kHz step input. Other systems refer to acquisition and lock times as the time the system takes to reduce the ...
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Clock Generator Module (CGM) 8.10.2 Parametric Influences on Reaction Time Acquisition and lock times are designed short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and ...
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Choosing a Filter Capacitor As described in external filter capacitor, C the PLL. The PLL is also dependent on reference frequency and supply voltage. The value of the capacitor must, therefore, be chosen with supply potential and reference frequency ...
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Clock Generator Module (CGM) The K factor in the equations is derived from internal PLL parameters. K ACQ K is the K factor when the PLL is configured in tracking mode. (See TRK 8.4.2.2 Acquisition and Tracking Note the inverse ...
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Technical Data — MC68HC708MP16 Section 9. Pulse Width Modulator for Motor Control 9.1 Contents 9.2 9.3 9.4 9.4.1 9.4.2 9.5 9.5.1 9.5.2 9.6 9.6.1 9.6.2 9.6.3 9.6.3.1 9.6.3.2 9.6.4 9.6.5 9.7 9.7.1 9.7.1.1 9.7.1.2 9.7.1.3 9.7.2 9.7.3 9.8 9.9 9.10 ...
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Pulse Width Modulator for Motor Control (PWMMC) 9.11 9.11.1 9.11.2 9.11.3 9.11.4 9.11.5 9.11.6 9.11.7 9.11.8 9.11.9 9.11.10 9.11.11 9.12 9.2 Introduction This section describes the pulse width modulator for motor control (PWMMC, Version A). The MC68HC(7)08MP16 PWM module can ...
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Features Features of the PWMMC include the following: • • • • • • • MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor Pulse Width Modulator for Motor Control (PWMMC) Pulse Width Modulator for Motor Control (PWMMC) Three complimentary PWM pairs ...
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Pulse Width Modulator for Motor Control (PWMMC) Addr. Name Read: PWM Control Register 1 $0020 Write: (PCTL1) Reset: Read: PWM Control Register 2 $0021 Write: (PCTL2) Reset: Read: Fault Control Register $0022 Write: (FCR) Reset: Read: FPIN4 Fault Status Register ...
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Addr. Name PWM Counter Modulo Register $0029 Low (PMODL) PWM 1 Value Register High $002A (PVAL1H) PWM 1 Value Register Low $002B (PVAL1L) PWM 2 Value Register High $002C (PVAL2H) PWM 2 Value Register Low $002D (PVAL2L) PWM 3 Value ...
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Pulse Width Modulator for Motor Control (PWMMC) Addr. Name Read: PWM 5 Value Register High $0032 Write: (PVAL5H) Reset: Read: PWM 5 Value Register Low $0033 Write: (PVAL5L) Reset: Read: PWM 6 Value Register High $0034 Write: (PVAL6H) Reset: Read: ...
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Timebase Refer to the following subsections for a discussion of the timebase. 9.4.1 Resolution In center-aligned mode, a 12-bit up/down counter is used to create the PWM period. Therefore, the PWM resolution in center-aligned mode is two clocks (highest ...
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Pulse Width Modulator for Motor Control (PWMMC) For edge-aligned mode, a 12-bit up-only counter is used to create the PWM period. Therefore, the PWM resolution in edge-aligned mode is one clock (highest resolution is125 Figure maximum count. ...
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Prescaler To permit lower PWM frequencies, a prescaler is provided which will divide the PWM clock frequency setting the prescaler bits in PWM control register 2 affects the PWM clock frequency. This prescaler ...
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Pulse Width Modulator for Motor Control (PWMMC) For ease of software, the LDFQx bits are buffered. When the LDFQx bits are changed, the reload frequency will not change until the previous reload cycle is completed. See NOTE: When reading the ...
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To prevent a partial reload of PWM parameters from occurring while the software is still calculating them, an interlock bit controlled from software is provided. This bit informs the PWM module that all the PWM parameters have been calculated, and ...
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Pulse Width Modulator for Motor Control (PWMMC) UP/DOWN COUNTER MODULUS = 3 PWM VALUE= 1 PWMF SET PWM UP/DOWN COUNTER LDOK = 1 MODULUS = 2 PWM VALUE = 1 PWMF SET PWM Technical Data 140 Pulse Width Modulator for ...
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MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor Pulse Width Modulator for Motor Control (PWMMC) Pulse Width Modulator for Motor Control (PWMMC) LDFQ1:LDFQ0 = 00 (RELOAD EVERY CYCLE) UP-ONLY COUNTER LDOK = 1 LDOK = 0 LDOK = 1 MODULUS = 3 ...
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Pulse Width Modulator for Motor Control (PWMMC) 9.5.2 PWM Data Overflow and Underflow Conditions The PWM value registers are 16-bit registers. Although the counter is only 12 bits, the user may write a 16-bit signed value to a PWM value ...
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PWM VALUE REG. PWM VALUE REG. PWM VALUE REG. AC INPUTS MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor Pulse Width Modulator for Motor Control (PWMMC) Pulse Width Modulator for Motor Control (PWMMC) PWMS 1 & 2 PWMS 3 & 4 PWMS ...
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Pulse Width Modulator for Motor Control (PWMMC) When complementary operation is used, two additional features are provided: • • If independent operation is chosen, each PWM has its own PWM value register. 9.6.2 Dead-Time Insertion As shown in be used ...
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OUTPUT CONTROL (OUTCTL) PWMPAIR12 (TOP) PWMPAIR34 (TOP) 6 PWMPAIR56 (TOP OUT2 OUT4 OUT6 MUX MUX PWM (TOP) PWM(TOP) DEAD-TIME PREDT(TOP) PREDT (TOP) POSTDT (TOP) OUTX OUTX ...
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Pulse Width Modulator for Motor Control (PWMMC) Whenever an input to a dead-time generator transitions, a dead-time is inserted (for example, both PWMs in the pair are forced to their inactive state). The BOTTOM PWM signal is generated from the ...
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UP/DOWN COUNTER MODULUS = 4 PWM VALUE = 2 PWM1 W/ NO DEAD-TIME PWM2 W/ NO DEAD-TIME PWM1 W/ DEAD-TIME=2 PWM2 W/ 2 DEAD-TIME=2 Figure 9-14. Effects of Dead-Time Insertion UP/DOWN COUNTER MODULUS = 3 PWM VALUE = 1 PWM1 ...
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Pulse Width Modulator for Motor Control (PWMMC) UP/DOWN COUNTER MOUDULUS = 3 PWM VALUE = 2 PWM1 W/ NO DEAD TIME PWM2 W/ NO DEAD TIME PWM1 W/ DEAD TIME = 3 PWM2 W/ 3 DEAD TIME = 3 Figure ...
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Top/Bottom Correction In a half-bridge AC motor drive, either the top or the bottom transistor controls the output voltage at any given time. The direction of the motor current determines which transistor controls the output. During deadtime, both transistors ...
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Pulse Width Modulator for Motor Control (PWMMC) During deadtime, load inductance distorts output voltage by keeping inductive current flowing through the diodes. Inductive distortion either lengthens or shortens the pulse width by one deadtime interval, depending on current direction. This ...
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To correct deadtime distortion, software can decrease or increase the value in the appropriate PWMVAL register. • • In complementary channel operation, the ISENS1–3 bits in PWM control register 1 select one of three correction methods: • • • ISENS[1:0] ...
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Pulse Width Modulator for Motor Control (PWMMC) 9.6.3.1 Manual Correction The IPOL1–IPOL3 bits select either the odd or the even PWM value registers to use in the next PWM cycle. NOTE: The IPOLx bits are buffered so that only one ...
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PWM TO TOP TRANSISTOR PWM TO BOTTOM TRANSISTOR LOAD VOLTAGE WITH HIGH POSITIVE CURRENT LOAD VOLTAGE WITH LOW POSITIVE CURRENT LOAD VOLTAGE ...
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Pulse Width Modulator for Motor Control (PWMMC) PWM1 PWM2 9.6.3.2 Automatic Correction The current sense pin, ISx, for a PWM pair selects either the odd or the even PWM value registers to use in the next PWM cycle. The selection ...
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PMCNT = PMMOD NOTE: The values latched on the ISx pins are buffered so that only one PWM register is used per PWM cycle current sense value changes during a PWM period, the new value does not take ...
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Pulse Width Modulator for Motor Control (PWMMC) 9.6.4 Output Polarity The output polarity of the PWMs is determined by two options: TOPNEG and BOTNEG. The top polarity option, TOPNEG, controls the polarity of PWMs 1, 3, and 5. The bottom ...
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Center-Aligned Positive Polarity UP/DOWN COUNTER MODULUS = 4 PWM <= 0 PWM = 1 PWM = 2 PWM = 3 PWM >= 4 Center-Aligned Negative Polarity UP/DOWN COUNTER MODULUS = 4 PWM <= 0 PWM = 1 PWM = 2 ...
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Pulse Width Modulator for Motor Control (PWMMC) 9.6.5 Output Port Control Conditions may arise in which the PWM pins need to be individually controlled. This is made possible by the PWM output control register (PWMOUT) shown in $0025 Read: Write: ...
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OUTx bit toggles as shown in is not inserted when the even OUTx bits change, there will be no dead- time violation as shown in Setting the OUTCTL bit does not disable the PWM generator and current sensing ...
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Pulse Width Modulator for Motor Control (PWMMC) UP/DOWN COUNTER MODULUS=4 DEAD-TIME = 2 PWM VALUE = 3 OUTCTL OUT1 OUT2 PWM1 PWM2 PWM1/PWM2 2 DEAD-TIME DEAD-TIME INSERTED AS PART OF NORMAL PWM OPERATION AS CONTROLLED BY CURRENT SENSING AND PWM ...
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FPIN2 (LOGIC HIGH FOR FAULT) TWO ONE FAULT SAMPLE SHOT PIN2 FILTER CLEAR BY WRITING 1 TO FTACK2 The example is of fault pin 2 with DISX. Fault pin 4 with DISY is logically similar and affects BANK Y disable. ...
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FPIN1 (LOGIC HIGH FOR FAULT) TWO ONE FAULT SAMPLE PIN1 SHOT FILTER CLEAR BY WRITING 1 TO FTACK1 The example is of fault pin 1. Fault ...
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To allow for different motor configurations and the controlling of more than one motor, the PWM disabling function is organized as two banks, bank X and bank Y. Bank information combines with information from the disable mapping register to allow ...
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Pulse Width Modulator for Motor Control (PWMMC) BANK X DISABLE BANK Y DISABLE 9.7.1 Fault Condition Input Pins A logic high level on a fault pin disables the respective PWM(s) determined by the bank and the disable mapping register. Each ...
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Fault Pin Filter Each fault pin incorporates a filter to assist in determining a genuine fault condition. After a fault pin has been logic low for one CPU cycle, a rising edge (logic high) will be synchronously sampled once ...
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Pulse Width Modulator for Motor Control (PWMMC) If the FINTx bit is set, a fault condition resulting in setting the corresponding FFLAG bit will also latch a CPU interrupt request. The interrupt request latch is not cleared until one of ...
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FILTERED FAULT PIN FILTERED FAULT PIN The function of the fault control and event bits is the same as in automatic mode except that the PWMs are not re-enabled until the FFLAGx event bit ...
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Pulse Width Modulator for Motor Control (PWMMC) 9.7.2 Software Output Disable Setting PWM disable bit DISX or DISY in PWM control register 1 immediately disables the corresponding PWM pins as determined by the bank and disable mapping register. The PWM ...
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Initialization and the PWMEN Bit For proper operation, all registers should be initialized and the LDOK bit should be set before enabling the PWM via the PWMEN bit. When the PWMEN bit is first set, a reload will occur ...
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Pulse Width Modulator for Motor Control (PWMMC) CPU CLOCK PWMEN HI-Z IF OUTCTL = 0 PWM PINS Figure 9-39. PWMEN and PWM Pins When the PWMEN bit is cleared, the following will occur: • • • When PWMEN is cleared, ...
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PWM Operation in Wait Mode When the microcontroller is put in low-power wait mode via the WAIT instruction, all clocks to the PWM module will continue to run interrupt is issued from the PWM module (via a ...
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Pulse Width Modulator for Motor Control (PWMMC) 9.11 Control Logic Block The following subsections provide a description of the control logic block. 9.11.1 PWM Counter Registers This PWM counter register displays the12-bit up/down or up-only counter. When the high byte ...
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PWM Counter Modulo Registers This PWM counter modulus register holds a 12-bit unsigned number that determines the maximum count for the up/down or up-only counter. In center-aligned mode, the PWM period will be twice the modulus (assuming no prescaler). ...
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Pulse Width Modulator for Motor Control (PWMMC) 9.11.3 PWM X Value Registers Each of the six PWMs has a 16-bit PWM value register. PVALXH Read: Write: Reset: PVALXL Read: Write: Reset: The 16-bit signed value stored in this register determines ...
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PWM Control Register 1 PWM control register 1 controls PWM enabling/disabling, the loading of new modulus, prescaler, and PWM values, and the PWM correction method. In addition, this register contains the software disable bits to force the PWM outputs ...
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Pulse Width Modulator for Motor Control (PWMMC) NOTE: The user should initialize the PWM registers and set the LDOK bit before enabling the PWM. A PWM CPU interrupt request can still be generated when LDOK is zero. ISENS1:ISENS0 — Current ...
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NOTE: When PWMINT is cleared, pending CPU interrupts are inhibited. DISX — Software Disable for Bank X This read/write bit allows the user to disable one or more PWM pins in bank X. The pins that are disabled are determined ...
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Pulse Width Modulator for Motor Control (PWMMC) LDFQ1:LDFQ0 — PWM Load Frequency Bits These buffered read/write bits select the PWM CPU load frequency according to NOTE: When reading these bits, the value read is the buffer value (not necessarily the ...
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NOTE: When reading this bit, the value read is the buffer value (not necessarily the value the output control block is currently using). PRSC1:PRSC0 — PWM Prescaler Bits These buffered read/write bits allow the PWM clock frequency to be modified ...
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Pulse Width Modulator for Motor Control (PWMMC) 9.11.7 PWM Disable Mapping Write-Once Register This write-once register holds an 8-bit value which determines which PWM pins will be disabled if an external fault or software disable occur. For a further description ...
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FINT1 — Fault 1 Interrupt Enable This read/write bit allows the CPU interrupt caused by faults on fault pin enabled. The fault protection circuitry is independent of this bit and will always be active fault ...
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Pulse Width Modulator for Motor Control (PWMMC) FINT3 — Fault 3 Interrupt Enable This read/write bit allows the CPU interrupt caused by faults on fault pin enabled. The fault protection circuitry is independent of this bit and ...
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Fault Status Register This read-only register indicates the current fault status. Address: Read: Write: Reset: FFLAG1 — Fault Event Flag 1 The FFLAG1 event bit is set within two CPU cycles after a rising edge on fault pin 1. ...
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Pulse Width Modulator for Motor Control (PWMMC) FFLAG3 — Fault Event Flag 3 The FFLAG3 event bit is set within two CPU cycles after a rising edge on fault pin 3. To clear the FFLAG3 bit, the user must write ...
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Fault Acknowledge Register This register is used to acknowledge and clear the FFLAGs. In addition used to monitor the current sensing bits to test proper operation. Address: Read: Write: Reset: FTACK1 — Fault Acknowledge 1 The FTACK1 ...
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Pulse Width Modulator for Motor Control (PWMMC) DT1 — Dead Time 2 Current sensing pin IS1 is monitored immediately before dead time ends due to the assertion of PWM2. DT1 — Dead Time 3 Current sensing pin IS2 is monitored ...
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The generator continues to run, but is no longer the input to the PWM dead-time and output circuitry. When OUTCTL is cleared, the outputs of the PWM generator immediately become the inputs to the dead- time and output circuitry. OUT6:OUT1— ...
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Pulse Width Modulator for Motor Control (PWMMC) 9.12 PWM Glossary CPU Cycle — One internal bus cycle (1/f PWM Clock Cycle (or Period) — One tick of the PWM counter (1/f with no prescaler). See PWM Cycle (or Period) • ...
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PWM Load Frequency — Frequency at which new PWM parameters get loaded into the PWM. See RELOAD NEW MODULUS, PRESCALER, & PWM VALUES IF LDOK = 1 MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor Pulse Width Modulator for Motor Control (PWMMC) ...
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Pulse Width Modulator for Motor Control (PWMMC) Technical Data 190 Pulse Width Modulator for Motor Control (PWMMC) MC68HC708MP16 Rev. 3.1 — Freescale Semiconductor ...
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Technical Data — MC68HC708MP16 10.1 Contents 10.2 10.3 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.2 Introduction This section describes the monitor ROM (MON08, Version B). The monitor ROM allows complete testing of the MCU through a single-wire interface with ...
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Monitor ROM (MON) 10.3 Features Features of the monitor ROM include the following: • • • • • • 10.4 Functional Description The monitor ROM receives and executes commands from a host computer. mode and communicate with a host computer ...
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MC145407 + 10 µ µ DB- NOTES: Position A — Bus clock = CGMXCLK ÷ CGMVCLK ÷ 4 Position B — Bus clock = CGMXCLK ÷ 2 ...
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Monitor ROM (MON) 10.4.1 Entering Monitor Mode Table 10 Enter monitor mode by either: • • The MCU sends a break signal (10 consecutive logic 0s) to the host computer, indicating that ...
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Table 10-2 monitor mode. Modes User Monitor 1. If the high voltage (V 10.4.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See $A5 BREAK The data transmit and receive rate can be ...
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Monitor ROM (MON) 10.4.3 Echoing As shown in received byte back to the PTA0 pin for error checking. SENT TO MONITOR ECHO Any result of a command appears after the echo of the last byte of the command. 10.4.4 Break ...
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Commands The monitor ROM uses the following commands: • • • • • • Table 10-3. READ (Read Memory) Command Description Read byte from memory Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of ...
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Monitor ROM (MON) Table 10-4. WRITE (Write Memory) Command Description Write byte to memory Operand Specifies 2-byte address in high byte:low byte order; low byte followed by data byte Data Returned None Opcode $49 Command Sequence SENT TO MONITOR WRITE ...
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Table 10-6. IWRITE (Indexed Write) Command Description Write to last address accessed + 1 Operand Specifies single data byte Data Returned None Opcode $19 Command Sequence SENT TO MONITOR IWRITE ECHO NOTE: A sequence of IREAD or IWRITE commands can ...
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Monitor ROM (MON) Table 10-8. RUN (Run User Program) Command Description Executes RTI instruction Operand None Data Returned None Opcode $28 Command Sequence SENT TO MONITOR 10.4.6 Baud Rate With a 4.9152-MHz crystal and the PTC2 pin at logic 1 ...