MC68HC708MP16CFU

Manufacturer Part NumberMC68HC708MP16CFU
ManufacturerFreescale Semiconductor, Inc
MC68HC708MP16CFU datasheet
 
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Page 108/398

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Clock Generator Module (CGM)
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f
Modulating the voltage on the CGMXFC pin changes the frequency
within this range. By design, f
frequency, f
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, f
buffer. The buffer output is the final reference clock, CGMRDV, running
at a frequency f
The VCO’s output clock, CGMVCLK, running at a frequency f
back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor, N. The dividers output is the VCO
feedback clock, CGMVDV, running at a frequency f
8.4.2.4 Programming the PLL
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the DC voltage on the external capacitor connected
to CGMXFC based on the width and direction of the correction pulse.
The filter can make fast or slow corrections depending on its mode,
described in
external capacitor and the reference frequency determines the speed of
the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency f
condition based on this comparison.
Technical Data
108
is equal to the nominal center-of-range
VRS
, (4.9152 MHz) times a linear factor L, or (L)f
NOM
, and is fed to the PLL through a
RCLK
= f
.
RDV
RCLK
for more information.)
8.4.2.2 Acquisition and Tracking
. The circuit determines the mode of the PLL and the lock
RDV
Clock Generator Module (CGM)
.
VRS
.
NOM
, is fed
VCLK
= f
/N. (See
VDV
VCLK
Modes. The value of the
MC68HC708MP16
Rev. 3.1
Freescale Semiconductor