MC68HC708MP16CFU

Manufacturer Part NumberMC68HC708MP16CFU
ManufacturerFreescale Semiconductor, Inc
MC68HC708MP16CFU datasheet
 
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Page 109/398

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8.4.2.2 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two
operating modes:
8.4.2.3 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. (See
interrupts are enabled, the software can wait for a PLL interrupt request
and then check the LOCK bit. If interrupts are disabled, software can poll
the LOCK bit continuously (during PLL start-up, usually) or at periodic
intervals. In either case, when the LOCK bit is set, the VCO clock is safe
to use as the source for the base clock. (See
Circuit.) If the VCO is selected as the source for the base clock and the
LOCK bit is clear, the PLL has suffered a severe noise hit and the
software must take appropriate action, depending on the application.
(See
MC68HC708MP16
Rev. 3.1
Freescale Semiconductor
Acquisition mode — In acquisition mode, the filter can make large
frequency corrections to the VCO. This mode is used at PLL start-
up or when the PLL has suffered a severe noise hit and the VCO
frequency is far off the desired frequency. When in acquisition
mode, the ACQ bit is clear in the PLL bandwidth control register.
(See
8.6.2 PLL Bandwidth Control
Tracking mode — In tracking mode, the filter makes only small
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. (See
8.4.3 Base Clock Selector
automatically in tracking mode when not in acquisition mode or
when the ACQ bit is set.
8.6.2 PLL Bandwidth Control
8.7 Interrupts
for information and precautions on using interrupts.)
Clock Generator Module (CGM)
Clock Generator Module (CGM)
Register.)
Circuit.) The PLL is
Register.) If PLL
8.4.3 Base Clock Selector
Technical Data
109