MC68HC708MP16CFU

Manufacturer Part NumberMC68HC708MP16CFU
ManufacturerFreescale Semiconductor, Inc
MC68HC708MP16CFU datasheet
 


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Page 112/398:

Base Clock Selector Circuit

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Clock Generator Module (CGM)
NOTE:
Exceeding the recommended maximum bus frequency or VCO
frequency can crash the MCU.
9. Program the PLL registers accordingly:
8.4.2.5 Special Programming Exceptions
The programming method described in
does not account for possible exceptions. A value of zero for N or L is
meaningless when used in the equations given. To account for these
exceptions:
8.4.3 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the
VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The
two input clocks go through a transition control circuit that waits up to
three CGMXCLK cycles and three CGMVCLK cycles to change from
one clock source to the other. During this time, CGMOUT is held in
stasis. The output of the transition control circuit is then divided by two
to correct the duty cycle. Therefore, the bus clock frequency, which is
one-half of the base clock frequency, is one-fourth the frequency of the
selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source
if the PLL is not turned on. The PLL cannot be turned off if the VCO clock
is selected. The PLL cannot be turned on or off simultaneously with the
Technical Data
112
a. In the upper four bits of the PLL programming register (PPG),
program the binary equivalent of N.
b. In the lower four bits of the PLL programming register (PPG),
program the binary equivalent of L.
A zero value for N is interpreted exactly the same as a value of
one.
A zero value for L disables the PLL and prevents its selection as
the source for the base clock. (See
Circuit.)
Clock Generator Module (CGM)
8.4.2.4 Programming the PLL
8.4.3 Base Clock Selector
MC68HC708MP16
Rev. 3.1
Freescale Semiconductor